CHAPTER 10: DMAC
498 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
[bit23] RC : Reload Count (BC/TC reload)
This bit controls the reload function of BC[3:0] and TC[15:0].
When this bit is set to "1", the value set when the transfer started is reloaded to BC[3:0] and TC[15:0]
upon completion of the transfer.
Disables the reload function of BC/TC. (Initial value)
Enables the reload function of BC/TC.
[bit22] RS : Reload Source
This bit controls the reload function of the transfer source address.
When this bit is set to "1", the value set when the transfer started is reloaded to DMACSA upon
completion of the transfer.
Disables the reload function of the transfer source address. (Initial value)
Enables the reload function of the transfer source address.
[bit21] RD : Reload Destination
This bit controls the reload function of the transfer destination address (DMACDA).
When this bit is set to "1", the value set when the transfer started is reloaded to DMACDA upon
completion of the transfer.
Disables the reload function of the transfer destination address. (Initial value)
Enables the reload function of the transfer destination address.
[bit20] EI :Error Interrupt (unsuccessful transfer completion interrupt enable)
This bit enables or disables the notification of an interrupt when a transfer has been unsuccessfully
completed.
When this bit is set to "1", an interrupt is issued if SS[2:0] is in the following status upon completion of the
transfer.
− Address overflow
− Stop by transfer stop request from a Peripheral, or the disabling of transfer by the EB/DE bit
− Transfer source access error
− Transfer destination access error
Disables an interrupt to be issued upon unsuccessful completion of transfer. (Initial value)
Enables an interrupt to be issued upon unsuccessful completion of transfer.
[bit19] CI :Completion Interrupt : (successful transfer completion interrupt enable)
This bit enables or disables the notification of an interrupt when a transfer has been successfully
completed.
When this bit is set to "1", an interrupt is generated, if SS[2:0] is set to successful completion upon
completion of the transfer.
Disables an interrupt to be issued upon successful completion of transfer.
(Initial value)
Enables an interrupt to be issued upon successful completion of transfer.
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