CHAPTER 2-2: Clock Gating
86 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
Explanation on Block Diagram
Peripheral Clock Gating Control Unit
The clock control or the reset control of each peripheral function is executed by changing the register
setting value via the APB2 bus. Be sure to rewrite this register with setting APB2 clock enable bit
(APBC2_PSR. APBC2EN) inAPB2 prescaler register (APBC2_PSR) of the clock control unit to the output
enable and permitting PCLK2 output.
The clock of each peripheral function stops when the bit field of the target function is set to "0". When the
bit field is set to 1, the clock is supplied. The initial value of a register is different by peripheral function.
For details, see Table 1-1.
The reset of each peripheral function is issued when the bit field of the target function is set to1. When the
bit field is set to 0, the reset is released. The initial value of each register is always 0 to release the reset.
Peripheral Clock Gating Logic
Internal bus clock (HCLK, PCLK1, PCLK2) is supplied or gated by each specific peripheral function
according to clock gating signal from the peripheral clock gating control unit.
Peripheral Reset Control Logic
The reset is individually controlled by each peripheral function according to the reset control signal from
the peripheral clock gating control unit. The reset control unit is the same with the peripheral clock control
unit. However, it does not exceptionally have the bit field of this reset control for I/O Port alone.
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