CHAPTER 14: External Bus Interface
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 815
[bit3:0] RACC: Read Access Cycle
These bits set the number of cycles required for read access.
Read access cycle will be used during (RACC+1) cycle.
The address remains unchanged during the cycle specified by these bits, and the data is captured at the
last cycle.
16 cycles [Initial value]
Notes:
− If you write a disabled value to a WWEC, WADC or WACC bit, the operation of the external bus
interface is not guaranteed.
− In NAND Flash memory read mode, the MNWEX and MNREX timings are set by the timing
registers as is the case with MWEX and MOEX.
− If "0" is set to RADC, MOEX and MCSX is asserted at the same time.
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