Cypress FM4 Series - Page 200

CHAPTER 6: Low Power Consumption Mode
200 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
PLL Mode Transition Diagram
In PLL mode, the PLL clock is used as the master clock.
Figure 2-6 PLL Mode Transition Diagram
PLL timer mode
STOP mode
Program reset
RTC mode
PLL oscillation stabilization
wait
Main mode
E-1 Transition to RUN mode (PLRDY = 1)
E-2 Start of PLL oscillation (PLRDY = 0)
E-1 E-2
E-4 Software reset
E-4
E-5
E-3
E-5 Release of software reset
E-3 End of oscillation stabilization wait
(PLRDY = 1)
E-8
E-7
E-6 SLEEP mode
(SLEEPDEEP = 0,
WFI/WFE instruction)
E-7 Interrupt
E-9
E-8 TIMER mode (SLEEPDEEP = 1, RTCE = 0,
DSTM = 0, STM = 00, WFI/WFE instruction)
E-15
E-10
E-10 STOP mode (SLEEPDEEP = 1, RTCE = 0,
DSTM = 0, STM = 10, WFI/WFE instruction)
E-15
E-11
E-11 Transition to main mode
Deep standby RTC mode
Release of deep standby
transition reset
E-14
E-12
E-13 Deep standby stop mode
(SLEEPDEEP = 1, RTCE = 0,
DSTM = 1, STM = 10, WFI/WFE instruction)
PLL sleep mode
E-6
E-7
E-9 RTC mode (SLEEPDEEP = 1, RTCE = 1,
DSTM = 0, STM = 10, WFI/WFE instruction)
Deep standby stop mode
E-13
High speed CR oscillation
stabilization wait and low speed
CR oscillation stabilization wait in
Figure 2-1
E-12 Deep standby RTC mode
(SLEEPDEEP = 1, RTCE = 1,
DSTM = 1, STM = 10, WFI/WFE instruction)
E-14 Deep standby return factor
E-14
PLL run mode
E-16
E-16 End of oscillation stabilization wait (MORDY = 1)
Deep standby transition reset
Deep standby transition reset
Main oscillation stabilization
wait
E-17
E-17
E-15 Interrupt (PINC = 0)
E-17 Interrupt (PINC = 1)