CHAPTER 8: Interrupts
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 355
Figure 2-1 illustrates how the NVIC is connected to the interrupt signals input from peripheral functions,
the DMAC and the DSTC. Details of the connection are explained below.
NVIC
The NVIC supports reserved system exceptions and 128 peripheral interrupts. For details of the NVIC,
refer to Cortex-M4 Technical Reference Manual. In Cortex-M4 Technical Reference Manual, an exception
other than the reserved system exceptions is defined as external interrupt (IRQ). In this document, the
external interrupt (IRQ) is called a peripheral interrupt to differentiate the external interrupt (IRQ) from the
external interrupt from a microcontroller external input pin.
The interrupt priority register of the NVIC has a 4-bit configuration and can set 16 interrupt priority levels.
The respective priorities of reserved system exception no. 4 to no. 15 can be set by using the System
Handler Priority Registers (addresses: 0xE000ED18, 0xE000ED1C, 0xE000ED20) installed in the NVIC.
The respective priorities of peripheral interrupts of exception no. 16 to no. 143 can be set by using the
IRQ Priority Registers (addresses: 0xE000E400 to 0xE000E47C) installed in the NVIC.
The NVIC supports non-maskable interrupt (NMI) input.
Interrupt Aggregation and Batch Read Registers
Interrupt signals to be input from all peripheral functions (Interrupt signals from peripheral functions in
Figure 2-1) are aggregated by the logic OR circuit in the figure. The aggregated interrupt signals are then
connected to one of the 128 peripheral interrupts of the NVIC. See Table 3-1 and Table 3-2 to check to
which peripheral function interrupt signal an interrupt output of the NVIC is assigned.
Since interrupt signals are aggregated by the logical OR circuit, one interrupt of the NVIC is generated by
multiple sources. When an interrupt is generated, the source that caused that interrupt can be identified
by reading Interrupt Batch Read Registers (IRQxxxMON Register in Figure 2-1). The Interrupt Batch
Read Registers (IRQ000MON to IRQ127MON) cover all interrupt inputs of the NVIC.
Each bit of IRQxxxMON register in the case of non-equipped in each product, is a reserved bit.The
non-maskable interrupt signals (NMI) from the external interrupt and NMI controllers, and the interrupt
signal (HW-Watchdog) from the hardware watchdog timer are aggregated by a logic OR circuit and then
connected to the input of exception no. 2 of the NVIC. When an interrupt of exception no. 2 is generated,
the source of the interrupt, which is either external interrupt and NMI controllers or hardware watchdog
timer, can be identified by reading the EXC02MON Register.
The NMI pin of the microcontroller is shared with a general-purpose port. After a reset has been released,
the initial function of the pin is general-purpose port, and NMI input is masked. To use the NMI function,
enable the NMI function using the I/O port setting. For details, see Chapter I/O Port. The NMI input
signals are input to the NVIC via the external interrupt and NMI controllers.
Interrupt Relocate Function
When an interrupt whose source is aggregated with other sources is generated, the interrupt source is
identified by the software. The identification of the interrupt source can be avoided by using the interrupt
relocate function (Interrupt relocation in Figure 2-1).
Select the interrupt that needs to be relocated with the Relocate Interrupt Select Register (IRQxxxSEL in
Figure 2-1). The interrupt signal selected is to be generated not at its original position but as a relocate
interrupt. As the interrupt signal selected is separated from the logical OR circuit and is input to the NVIC
independently of other interrupt signals, it can be processed by another interrupt vector. Since it is no
longer necessary to identify an interrupt source, the NVIC can execute interrupt processing more
efficiently. There are eight relocate interrupts, IRQ003 to IRQ010, available in the NVIC.
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