CHAPTER 8: Interrupts
356 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
DMAC Transfer Request Connection Selection
Certain interrupt signals from peripheral functions can be used as DMA transfer request signals to the
DMAC. The output selector circuit (SEL in Figure 2-1) determines whether such interrupt signals are
connected to the NVIC or are connected to the DMAC as DMA transfer request signals (IDREQ to DMAC
in Figure 2-1). Change the SEL1 setting with the DRQSEL Register. For details of the DMAC, see chapter
DMAC.
If an interrupt signal is connected to the DMAC by the SEL1, the DMA transfer of the DMAC can be
started. In this situation, the signal to the NVIC is fixed at Low level. The bit corresponding to that interrupt
signal in the IRQxxxMON Register reads 0 and no interrupt is generated to the NVIC. In addition, no
transfer request notification is sent to the DSTC.
DSTC Transfer Request and DSTC Transfer End interrupt Connection Selection
There are two types of peripheral functions using DMA transfer of DSTC; one is the interrupt signal and
DMA transfer request signal is combined for sharing use,( This is abbreviated “Combined type”.) and
another is handling them separately.(This is abbreviated “Separated type”.) Separated type peripheral
functions hold the DSTC transfer requests separately from interrupts. Separated type peripheral functions
are I2S, HS-SPICNT, CAN-FD and programmable CRC. The setting value of the DREQENB[255:0]
register and the SE2, SEL3 in this figure switch the operations as follows.
Case of the Combined type:
When DREQENB[n]=0;
Interrupt signal from peripheral is inputted to the NVIC, notify interrupt.
Interrupt signal from peripheral is ignored by the DSTC.
HWINT[n] signals from DSTC are not inputted to NVIC. HWINT[n] is the output signal for interrupt
from the DSTC to the CPU, and is used to for notification of a HW transfer completion of the
DSTC.
When DREQENB[n]=1;
Interrupt signal from peripheral is not inputted to the NVIC.
Interrupt signal from peripheral is inputted to the DSTC, and the DSTC start the DMA transfer by
this signals.
HWINT[n] signals from DSTC are inputted to NVIC, instead of interrupt signal from peripheral.
In the case of this type, the input port of NVIC is shared to use the interrupt from peripheral and HWINT[n]
interrupt of the transfer completion from the DSTC. With this configuration, in the process of the NVIC, an
interrupt from a peripheral, and a transfer completion interrupt from the DSTC jump to the same interrupt
vector. Therefore, use the DREQENB[n] register to choose the interrupt to be processed. Because of the
circuit configuration as shown in the figure, the transfer completion interrupts from DSTC can be read
from the corresponding bit of the IRQxxxMON register. In addition, interrupt relocate function can be
applied.
Case of the Separated type:
When DREQENB[n]=0;
Interrupt signal from peripheral is inputted to the NVIC, notify interrupt.
Interrupt signal from peripheral is not inputted to the DSTC.
Transfer request signal from peripheral is not inputted to the NVIC
Transfer request signal from peripheral is ignored by the DSTC
HWINT[n] from the DSTC is inputted to the NVIC. (not asserted ).
When DREQENB[n]=1;
Interrupt signal from peripheral is inputted to the NVIC, notify interrupt.
Interrupt signal from peripheral is not inputted to the DSTC.
To Next Page
Loading...
