CHAPTER 6: Low Power Consumption Mode
224 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
Return from Deep Standby Stop Mode
The CPU returns from deep standby stop mode in one of the following situations.
Return due to resets, interrupts and WKUP pin input
If a reset (INITX pin input reset or low voltage detection reset) occurs, or the CPU receives a request for
an effective low voltage detection interrupt or for WKUP pin input, the CPU returns from deep standby
stop mode, and regardless of the clock mode, switches to high speed CR run mode on a deep standby
transition reset.
In deep standby stop mode, since the software watchdog reset, the hardware watchdog reset, the clock
supervisor reset and the anomalous frequency detection reset are not available, these resets cannot be
used to make the CPU return from deep standby stop mode.
Oscillation stabilization wait at return
On returning from deep standby RTC mode, regardless of the return factor, the CPU waits for the
stabilization of high speed CR clock oscillation and that of low speed CR clock oscillation.
Built-in regulator voltage stabilization wait at return
The CPU automatically secures a voltage stabilization wait time (a few hundred s) for the operation
mode transition of the built-in regulator before returning from deep standby stop mode. After the voltage
stabilization wait time has lapsed, the CPU executes the return operation.
Notes:
− Before making the CPU transit to deep standby stop mode, ensure that no factor for returning
from deep standby stop mode shown in Table 5-2 has been set. ( include the interrupt pending
register in the NVIC) If such factor has been set, clear that factor.
− If the CPU transits to deep standby stop mode during debugging, as the clock supply to the CPU
stops, the CPU cannot return to a Run mode by using the ICE. Use a reset, an interrupt or WKUP
pin input to make the CPU return to a Run mode.
− Before making the CPU transit to deep standby stop mode, ensure that the Flash memory
automatic algorithm has terminated.
− For TYPE1-M4 and TYPE2-M4 products, in the case of disabling the CPU returning from a deep
standby mode due to LVD interrupt, set the LVD interrupt return enable bit(WLVDE) in the Deep
Standby Return Enable Register (WIER) and Low-voltage detection interrupt enable bit(LVDIE) in
the Low-voltage Detection Voltage Control Register(LVD_CTL) to 0.
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