CHAPTER 2-1: Clock
80 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
− If the standby mode is released by an interrupt, the device restarts in the clock mode that indicated
by the RCS[2:0] bits in the SCM_CTL register.
− If any reset occurs other than software resets, the high-speed CR clock (CLKHC) is set as a master
clock. High-speed CR clock mode is set as clock mode.
− If any reset other than software resets is executed, the main clock and sub clock oscillators, and
PLL oscillation stop. If you want to use those oscillators again after the reset, enable them using the
SCM_CTL register.
− For the correlation between each clock mode and start/stop of the oscillator, see Chapter Low
Power Consumption Mode.
− For clock stop functions for each peripheral function, see Peripheral Clock Gating.
− To turn off the power supply on the chip side and operate only VBAT domain, be sure to set
WTOSCCNT.SOSCNTL=0 and then turn off the power supply on the chip side.
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