CHAPTER 11: DSTC
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 521
ACK[1:0]
ACK[1:0] (Acknowledge) sets the value for adjusting the timing of DSTC outputting the DMA transfer
request acknowledge signal to a peripheral device when the HW transfer is used.
If the HW transfer is used, set ACK to 01 for a DES to be directly started by the HW Start from a
peripheral device. For other DES (the DES started by the Chain Start from the HW transfer, the DES used
in the SW transfer, and the DES started by the Chain Start from the SW transfer), set ACK to 00.
DMSET
The DMSET (DMA request mask set) provides a function that sets the DQMSK[n] Register and masks a
DMA transfer request signal from a peripheral during the period between the time at which the DSTC
finishes the DES close process and the time at which the CPU finishes rebuilding the DES. For details,
see " 3.2.4 Control of HW Transfer".
If the HW transfer is used, the DMA transfer request signal (DREQ) from a peripheral is negated by the
DMA transfer request acknowledge signal (DACK) after the transfer has ended. However, depending on
peripherals, the DREQ is asserted at the following transfer request regardless of the status of the DSTC.
If the DREQ is asserted during the period between the time at which the DSTC finishes the DES close
process and the time at which the start of the next transfer is ready (rebuilding the DES), the DSTC
notifies the CPU of a DES open error because the start of the next transfer is not ready. In this situation,
setting the DMSET bit in Descriptor 0 to 1 can prevent the DSTC from notifying the CPU of a DES open
error, and can suppress the start of an HW Start transfer until the completion of rebuilding a DES.
Figure 3-4 shows an operation example.
If DMSET = 1 in the DES0 that is processed by the HW transfer directly from a peripheral, or that is
started by the Chain Start from HW transfer, when the DES close process is executed, the bit
corresponding to HW channel in the DQMSK[n] register is set to 1. (*1 in Figure 3-4) After that channel
bit has been set to 1, the DSTC does not recognize the DREQ[n] signal, and does not notify the CPU of
the DES open error. After the CPU has rebuilt the DES (*2 in Figure 3-4) and the next transfer is ready,
the CPU clears the channel bit in the DQMSK[n] Register. (*3 in Figure 3-4) After the CPU has cleared the
channel bit in the DQMSK[n] Register, the DSTC recognizes the DREQ[n] signal. A new transfer is started
according to the DES rebuilt by the CPU.
Figure 3-4 Using DMSET to Suppress Transfer Start
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