Cypress FM4 Series - Page 83

CHAPTER 2-2: Clock Gating
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 83
Overview of Connection with Clock and Reset Generation Units
Figure 1-1 shows the connection between peripheral clock gating and clock generation unit or reset
generation unit. The peripheral clock gating exists between peripheral function and clock generation unit
or reset generation unit and gates clocks and controls resets in the unit of peripheral function. When the
internal bus clock supply from the reset control units are stopped, the priority is given to the settings of the
clock control unit and the operation clock supplies to peripheral functions are gated To use the peripheral
clock gating, be sure to make the settings which enable the output of APB2 bus clock (PCLK2) in the
clock generation unit to control the rest.
Figure 1-1 Clock/Reset Connection related to Peripheral Clock Gating
Clock Generation Unit*3
Reset Generation Unit*4
Base Clock(HCLK)
HCLK Operation
Peripheral
Function(01)
Gating
*1
Reset
*2
Peripheral
Function(02)
Gating
*1
Reset
*2
PCLK1 Operation
Peripheral
Function(11)
Gating
*1
Reset
*2
Peripheral
Function(12)
Gating
*1
Reset
*2
PCLK2 Operation
Peripheral
Function(21)
Gating
*1
Reset
*2
Peripheral
Function(22)
Gating
*1
Reset
*2
HRESET
PRESET1
PRESET2
PCLK1
PCLK2
Peripheral Clock Gating
Control Unit
Operation Clock
Setting Reset
Clock Gating Signal
*1
Reset Control
Signal
*2
AHB Bus
APB1 Bus
APB2 Bus
*1: Clock gating (internal bus clock gating) in the unit of peripheral function
*2: Forcible reset or bus reset (see Chapter "Reset") by peripheral function unit
*3: For details, see Chapter Clock.
*4: For details, see Chapter Reset.