CHAPTER 10: DMAC
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 487
Description of Each State
Disable state
See the hardware transfer (EM=0) procedure.
Wait-1st-trigger state
See the hardware transfer (EM=0) procedure.
Transfer state
In this state, the channel to be controlled has received the first transfer request from the
Peripheral. A channel in this state performs transfer operation as specified. In the case of EM=1, it
moves to Wait-1st-trigger state, once all the transfer operation is completed. It also changes its
state upon instruction from CPU.
Pause state
See the hardware transfer (EM=0) procedure.
Explanation of Control Procedure
1. Disable state / Preparation for transfer
See Step 1 in the hardware transfer (EM=0) procedure.
To set EM=1, set all of the reload specifications for the transfer content (RC, RS, RD) in order to
prevent data transfer in an unintended address area. Also, CI is not set, because it is
meaningless to generate a successful transfer completion interrupt from DMAC. EI is set to
generate an unsuccessful transfer completion interrupt from DMAC.
2. Disable state => Wait-1st-trigger state / Enabling transfer
See Step 2 in the hardware transfer (EM=0) procedure.
3. Wait-1st-trigger state / Start of transfer
See Step 3 in the hardware transfer (EM=0) procedure.
4. Transfer state
See Step 4 in the hardware transfer (EM=0) procedure.
5. Transfer state => Wait-1st-trigger state / Successful completion of transfer
When transfers are successfully completed for the number of times calculated by (BC+1)×
(TC+1), the channel in Transfer state does not clear EB but does clear PB and ST and moves to
Wait-1st-trigger. It sets SS[2:0]=101 to provide the notification of the successful completion. As CI
is not set, no successful transfer completion interrupt is generated. Since RC, RS and RD are set,
the specifications of the transfer content of BC, TC, DMACSA and DMACDA are reloaded.
6. Transfer state => Wait-1st-trigger state / Transfer error end
See Step 6 in the hardware transfer (EM=0) procedure.
In the case of EM=1, EB is not cleared even if the transfer ends due to an error. It clears PB and
ST, moves to Wait-1st-trigger state and waits for the next transfer request. Therefore, it is
recommended not to use DMA transfer with EM=1 in an address area where a transfer error may
occur.
7. Transfer state =>Wait-1st-trigger state /End of Peripheral stop request
See Step 7 in the hardware transfer (EM=0) procedure.
In the case of EM=1, EB is not cleared even if a stop request is issued from the Peripheral. It
clears PB and ST and moves to Wait-1st-trigger state. Since RC, RS and RD are set, the
specifications of the transfer content of BC, TC, DMACSA and DMACDA are reloaded. As EI is
set, an unsuccessful transfer completion interrupt is generated.
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