CHAPTER 10: DMAC
488 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
8. Wait-1st-trigger state / Post-transfer process
In the case of EM=1, EB is not cleared upon the completion of the transfer. (DE=1, EB=1,
DH=0000, PB=0) is set and it moves to Wait-1st-trigger state. When the next transfer request is
generated from the Peripheral, therefore, the next transfer starts without an instruction from CPU.
If it moves to Wait-1st-trigger state due to a stop request from the Peripheral, an unsuccessful
completion interrupt occurs and that state can be confirmed. Also, the transfer request signal is
masked while the stop request signal is asserted. Even if the next transfer request signal is
asserted from the Peripheral, it will not be recognized and the channel to be controlled will remain
in Wait-1st-trigger state, waiting for an instruction from CPU.
In the above case, SS[2:0] is read from CPU to check the state of the transfer completion. The
interrupt signal is deasserted by clearing SS[2:0] from CPU. CPU clears EB and it returns to
Disable state (this operation is the operation shown in Step 15 of the hardware transfer (EM=1)
procedure). The transfer request signal and the stop request signal from the Peripheral are
deasserted, as shown in Step 7 of the hardware transfer (EM=0) procedure
9. Transfer state => Disable state / Completion of transfer by EM=0
The operation can exit from the loop of Wait-1st-trigger state and Transfer state by writing EM=0
from CPU. At the timing when the transfer stops after the instruction, EB, ST and PB are cleared
and the Transfer state changes to Disable state (DE=1, EB=0, DH=0000, PB=0) to successfully
complete the transfer. In this case, no successful transfer completion interrupt is generated, as CI
is not set.
10. Transfer state, Pause state => Disable state / Forced termination of transfer
See Step 8 in the hardware transfer (EM=0) procedure.
The operation can exit from the loop of Wait-1st-trigger state and Transfer state by an operation
disable instruction. When an instruction to disable individual-channel operation is issued, the
relevant channel moves to Disable state (DE=1, EB=0, DH=0000, PB=0) and stops the operation.
When an instruction to enable all-channel operation is issued, it moves to Disable state (DE=0,
EB=1, DH=0000, PB=0) and stops the operation. In the case of an instruction to disable
all-channel operation, EB is not cleared either; therefore, attention must be paid.
When the operation exits from Transfer state, an unsuccessful transfer completion interrupt
occurs because it is unsuccessful completion due to the forced stop. When it exits from
Wait-1st-trigger state, the enabled transfer is cancelled (this operation is the operation shown in
Step 15 of the hardware transfer (EM=1) procedure).
11. Disable state / Post-transfer processing
See Step 9 in the hardware transfer (EM=0) procedure.
12. Transfer state, Pause state / Transfer pause
See Step 10 in the hardware transfer (EM=0) procedure.
13. Pause state
See Step 11 in the hardware transfer (EM=0) procedure.
14. Pause state / Cancellation of transfer pause
See Step 12 in the hardware transfer (EM=0) procedure.
15. Operation in Disable state and Wait-1st-trigger state
See Step 13 in the hardware transfer (EM=0) procedure.
In the case of EM=1, the Transfer state changes directly to Wait-1st-trigger state. Therefore, the
specifications of the transfer content cannot be rewritten during the repeated transfer operation
(rewriting the registers DMACSA, DMACDA, DMACB[31:1] and DMACA[28:0]).
To Next Page
Loading...
