CHAPTER 10: DMAC
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 489
− Additional Matter 1
See Additional Matter 1 in the hardware transfer (EM=0) procedure.
− Additional Matter 2
See Additional Matter 2 in the hardware transfer (EM=0) procedure.
In the case of EM=1, Additional Matter 2 does not apply, because EB is not cleared during the
transfer operation.
− Additional Matter 3
See Additional Matter 3 in the hardware transfer (EM=0) procedure.
− Additional Matter 4
See Additional Matter 4 in the hardware transfer (EM=0) procedure.
The following explains what must be noted when setting interrupts from DMAC with EM=1. As the
target channel does not change from Wait-1st-trigger state due to an unsuccessful completion
interrupt by a stop request from the Peripheral, the interrupt signal is not deasserted until it is
cleared from CPU. Similarly, as the target channel moves to Disable state due to an unsuccessful
transfer completion interrupt by a stop request from software, the interrupt signal is not
deasserted until it is cleared from CPU. Other successful transfer completion interrupts and
unsuccessful transfer completion interrupts may be deasserted at a timing that is not intended by
CPU, if the relevant channel moves to Transfer state. Therefore, attention must be paid.
− Additional Matter 5
See Additional Matter 5 in the hardware transfer (EM=0) procedure.
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