Cypress FM4 Series - Page 748

CHAPTER 13: CRC (Cyclic Redundancy Check)
748 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
Use Example 4 CRC32, Byte Order: Little Endian
Figure 2-5 Use Example 4 (CRC32, Byte Order: Little Endian)
//**********************************************
// CRC32 (IEEE-802.3)
// polynomial: 0x04C11DB7
// initial value: 0xFFFF_FFFF
// CRCCR.CRC32 1 // CRC32
// CRCCR.LTLEND: 1 // little endian
// CRCCR.LSBFST: 1 // LSB First
// CRCCR.CRCLTE: 1 // CRC little endian
// CRCCR.CRCLSF: 1 // CRC LSB First
// CRCCR.FXOR: 1 // CRC Final XOR on
//**********************************************
//
// Example 4-1 (CRC32)
//
// Initialization
B_WRITE (CRCCR, 0x7F);
// data write 0x313233343536373839
W_WRITE (CRCIN, 0x34333231);
W_WRITE (CRCIN, 0x38373635);
B_WRITE (CRCIN, 0x39);
// read result
W_READ (CRCR, data);
// check result
assert (data == 0xCBF43926); // <- little endian & LSB First
(Assumed as follows)
B_WRITE -- Byte writing
H_WRITE -- Half-word writing
W_WRITE -- Word writing
B_READ -- Byte reading
H_READ -- Half-word reading
W_READ -- Word reading
CRCCR -- CRC Control Register address
CRCINIT -- Initial Value Register address
CRCIN -- Input Data Register address
CRCR -- CRC Register address
CRC computing unit input sequence image
3
3
3
2
3
4
3
1
3
3
3
6
3
8
7
5
3
9
9
6
D
0
2
B
3
C
C
F
3
9
2
B
4
6
Head
Head
CRC result(in macro)
CRC output(FXOR & rearrange)
− In CRC32 (IEEE-802.3) mode, the bit order is set to LSB First. This CRC computing unit supports
both the big endian and little endian as the byte order. Figure 2-5 shows an example for little
endian.
− If bit inversion is not required for the CRC result, perform either one of the following processes to
release the bit inversion for the current result.
− Before calculation, Initialize with CRCCR=0x3F (CRCCR:FXOR=0, CRCCR:INIT=1).
− After data was input, set the CRCCR=0x3E (CRCCR:FXOR=0, CRCCR:INIT=0).