Cypress FM4 Series - Page 746

CHAPTER 13: CRC (Cyclic Redundancy Check)
746 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
Use Example 2 CRC16, Different Input Bit Widths Mixed
Figure 2-3 Use Example 2 (CRC16, Different Input Bit Widths Mixed, Core Byte Order: Big Endian)
//*********************************************
// CRC16 (CRC ITU-T)
// polynomial: 0x1021
// initial value: 0xFFFF
// CRCCR.CRC32: 0 //CRC16
// CRCCR.LTLEND: 0 //big endian
// CRCCR.LSBFST: 0 //MSB First
// CRCCR.CRCLTE: 0 //CRC big endian
// CRCCR.CRCLSF: 0 //CRC MSB First
// CRCCR.FXOR: 0 //CRC Final XOR off
//*********************************************
//
// Example 2-1 Writing widths mixed
//
// Initialization
B_WRITE (CRCCR, 0x01);
// data write 0x313233343536373839
W_WRITE (CRCIN, 0x31323334);
H_WRITE (CRCIN, 0x3536);
H_WRITE (CRCIN+2, 0x3738);
B_WRITE (CRCIN+3, 0x39);
// read result
H_READ (CRCR+2, data);
// check result
assert (data == 0x29B1);
//
// Example 2-2 CRC check
//
// Initialization
B_WRITE (CRCCR, 0x01);
// data write 0x313233343536373839 + CRC
W_WRITE (CRCIN, 0x31313334);
W_WRITE (CRCIN, 0x35363738);
H_WRITE (CRCIN, 0x3929); // <-- CRC(0x29)
B_WRITE (CRCIN, 0xB1); // <-- CRC(0xB1)
// read result
H_READ (CRCR+2, data);
// check result
assert (data == 0x0000);
(Assumed as follows)
B_WRITE -- Byte writing
H_WRITE -- Half-word writing
W_WRITE -- Word writing
B_READ -- Byte reading
H_READ -- Half-word reading
W_READ -- Word reading
CRCCR -- CRC Control Register address
CRCINIT -- Initial Value Register address
CRCIN -- Input Data Register address
CRCR -- CRC Register address
CRC computing unit input sequence image
MSB
LSB
3
3
3
3
3
3
3
3
3
3
1
5
7
9
2
6
8
4
− If the byte or bit order setting is correct and the bit input sequence to the CRC computing unit is the
same, the writing width can be specified arbitrarily.
For example, if a 1-, 2-, or 3-byte fraction is finally obtained in the word-base writing mode, both
byte and half-word writings may be enabled.