Cypress FM4 Series - Page 103

CHAPTER 2-2: Clock Gating
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 103
[bit17:16] I2SCK[1:0]: Settings for operation clock supply and gating of I
2
S Interface
These bits control the operation clock supply and gating to I
2
S Interface. The correspondence between
each bit and the I
2
S Interface channel is shown below.
bit16 – I2SCK0: I
2
S Interface channel 0
bit17 – I2SCK1: I
2
S Interface channel 1
When the relevant bit is set to 1, the bus clock is supplied to the corresponding I
2
S Interface channel to
use the I
2
S Interface function. For products to which the relevant I
2
S Interface channel is not mounted, it
is prohibited to change the relevant bit from the initial value.
When the relevant bit is set to 0, the bus clock input to the corresponding I
2
S Interface channel is gated.
While the bus clock input is gated, the I
2
S Interface function of the corresponding channel cannot be used
bit
Description
0
Gates the bus clock input to the I
2
S Interface channel corresponding to the relevant bit. (Initial value)
1
Supplies the bus clock to the I
2
S Interface channel corresponding to the relevant bit.
[bit15:14] IISCCK[1:0]: Settings for operation clock supply and gating of MFS I
2
S
Interface
These bits control the operation clock supply and gating to MFS I
2
S Interface. The correspondence
between each bit and the MFS I
2
S Interface channel is shown below.
bit14 – IISCCK0: MFS I
2
S Interface channel 0
bit15 – IISCCK1: MFS I
2
S Interface channel 1
When the relevant bit is set to 1, the bus clock is supplied to the corresponding MFS I
2
S Interface channel
to use the I
2
S Interface function. For products to which the relevant MFS I
2
S Interface channel is not
mounted, it is prohibited to change the relevant bit from the initial value.
When the relevant bit is set to 0, the bus clock input to the corresponding MFS I
2
S Interface channel is
gated. While the bus clock input is gated, the MFS I
2
S Interface function of the corresponding channel
cannot be used
bit
Description
0
Gates the bus clock input to the MFS I
2
S Interface channel corresponding to the relevant bit. (Initial
value)
1
Supplies the bus clock to the MFS I
2
S Interface channel corresponding to the relevant bit.
[bit13:12] ICCCK[1:0]: Settings for operation clock supply and gating of Smart Card
Interface
These bits control the operation clock supply and gating to Smart Card Interface. The correspondence
between each bit and the Smart Card Interface channel is shown below.
bit12 – ICCCK0: Smart Card Interface channel 0
bit13 – ICCCK1: Smart Card Interface channel 1
When the relevant bit is set to 1, the bus clock is supplied to the corresponding Smart Card Interface
channel to use the I
2
S Interface function. For products to which the relevant Smart Card Interface channel
is not mounted, it is prohibited to change the relevant bit from the initial value.
When the relevant bit is set to 0, the bus clock input to the corresponding Smart Card Interface channel is
gated. While the bus clock input is gated, the Smart Card Interface function of the corresponding channel
cannot be used.
bit
Description
0
Gates the bus clock input to the Smart Card Interface channel corresponding to the relevant bit. (Initial
value)
1
Supplies the bus clock to the Smart Card Interface channel corresponding to the relevant bit.