Contents
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 15
4.31. IRQ091 Batch Read Register (IRQ091MON) ............................................................... 422
4.32. IRQ092/093/094/095 Batch Read Register (IRQxxxMON) ........................................... 423
4.33. IRQ102 Batch Read Register (IRQ102MON) ............................................................... 424
4.34. IRQ112 Batch Read Register (IRQ112MON) ............................................................... 425
4.35. IRQ115 Batch Read Register (IRQ115MON) ............................................................... 427
4.36. IRQ117 Batch Read Register (IRQ117MON) ............................................................... 428
4.37. IRQ118 Batch Read Register (IRQ118MON) ............................................................... 429
4.38. IRQ119 Batch Read Register (IRQ119MON) ............................................................... 430
4.39. IRQ116 Batch Read Register (IRQ116MON) ............................................................... 431
4.40. USB ch.0 Odd Packet Size DMA Enable Register (ODDPKS) ..................................... 432
4.41. USB ch.1 Odd Packet Size DMA Enable Register (ODDPKS1) ................................... 434
5. Usage Precautions ...................................................................................................................... 436
CHAPTER 9: External Interrupt and NMI Control Sections .................................................................. 437
1. Overview ...................................................................................................................................... 438
2. Block Diagram ............................................................................................................................. 438
3. Operations and Setting Procedure Examples .............................................................................. 439
3.1. Operations of external interrupt control section .............................................................. 440
3.2. Operations of NMI control section .................................................................................. 442
3.3. Returning from timer or stop mode ................................................................................. 443
4. Registers ..................................................................................................................................... 444
4.1. External Interrupt Enable Register (ENIR) ...................................................................... 445
4.2. External Interrupt Factor Register (EIRR) ....................................................................... 446
4.3. External Interrupt Factor Clear Register (EICL) .............................................................. 447
4.4. External Interrupt Factor Level Register (ELVR) ............................................................ 448
4.5. External Interrupt Factor Level Register 1 (ELVR1) ....................................................... 449
4.6. Non Maskable Interrupt Factor Register (NMIRR) .......................................................... 450
4.7. Non Maskable Interrupt Factor Clear Register (NMICL) ................................................. 451
4.8. External Interrupt Factor Level Register 2 (ELVR2) ....................................................... 452
CHAPTER 10: DMAC ............................................................................................................................... 453
1. Overview of DMAC ...................................................................................................................... 454
2. Configuration of DMAC ................................................................................................................ 455
2.1. DMAC and System Configuration ................................................................................... 456
2.2. I/O Signals of DMAC ...................................................................................................... 458
3. Functions and Operations of DMAC ............................................................................................ 460
3.1. Software-Block Transfer ................................................................................................. 461
3.2. Software-Burst Transfer ................................................................................................. 463
3.3. Hardware-Demand Transfer ........................................................................................... 464
3.4. Hardware-Block Transfer & Burst Transfer ..................................................................... 465
3.5. Channel Priority Control ................................................................................................. 467
4. DMAC Control ............................................................................................................................. 468
4.1. Overview of DMAC Control............................................................................................. 469
4.2. DMAC Operation and Control Procedure for Software Transfer ..................................... 470
4.3. DMAC Operation and Control Procedure for Hardware (EM=0) Transfer ....................... 477
4.4. DMAC Operation and Control Procedure for Hardware (EM=1) Transfer ....................... 486
5. Registers of DMAC ...................................................................................................................... 490
5.1. List of Registers .............................................................................................................. 491
5.2. Entire DMAC Configuration Register (DMACR).............................................................. 492
5.3. Configuration A Register (DMACA) ................................................................................ 494
5.4. Configuration B Register (DMACB) ................................................................................ 497
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