Contents
18 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
4.40. Extended Pin Function Setting Register 35 (EPFR35) ................................................. 732
4.41. Special Port Setting Register (SPSR) ........................................................................... 734
4.42. Port Pseudo Open Drain Setting Register (PZRx) ........................................................ 736
4.43. Port Drive capability Select Register (PDSRx) ............................................................. 738
5. Usage Precautions ...................................................................................................................... 739
CHAPTER 13: CRC (Cyclic Redundancy Check) .................................................................................. 741
1. Overview of CRC ......................................................................................................................... 742
2. CRC Operations .......................................................................................................................... 743
2.1. CRC calculation sequence ............................................................................................. 744
2.2. CRC use examples ......................................................................................................... 745
3. CRC Registers ............................................................................................................................. 749
3.1. CRC Control Register (CRCCR) ..................................................................................... 750
3.2. Initial Value Register (CRCINIT) ..................................................................................... 752
3.3. Input Data Register (CRCIN) .......................................................................................... 753
3.4. CRC Register (CRCR) .................................................................................................... 754
CHAPTER 14: External Bus Interface .................................................................................................... 755
1. Overview of External Bus Interface ............................................................................................. 756
2. Block Diagram ............................................................................................................................. 758
3. Operations ................................................................................................................................... 761
3.1. Bus Access Mode ........................................................................................................... 762
3.2. SRAM and NOR Flash Memories Access ...................................................................... 767
3.3. NAND Flash memory access.......................................................................................... 769
3.3.1. Read access to NAND Flash memory ............................................................. 770
3.3.2. Write (auto program) access ............................................................................ 771
3.3.3. Auto block erase access .................................................................................. 772
3.4. Issue of an 8-bit NAND Flash memory read/write command .......................................... 773
3.5. 8-bit NAND Flash memory status read ........................................................................... 774
3.6. 8-bit NAND Flash memory data write ............................................................................. 775
3.7. Automatic Wait Setup ..................................................................................................... 776
3.8. External RDY .................................................................................................................. 781
3.9. SDRAM Access .............................................................................................................. 782
3.10. Interrupt Function ......................................................................................................... 788
3.11. Access Mode ................................................................................................................ 789
3.12. SDRAM buffer read (TYPE3-M4, TYPE4-M4, TYPE5-M4, TYPE6-M4 products) ........ 792
4. Connection Examples .................................................................................................................. 794
5. Setup Procedure Example ........................................................................................................... 799
6. Registers ..................................................................................................................................... 803
6.1. Mode 0 Register to Mode 7 Register (MODE0 to MODE7) ............................................ 804
6.2. Timing Register 0 to Timing Register 7 (TIM0 to TIM7) .................................................. 812
6.3. Area Register 0 to Area Register 7 (AREA0 to AREA7) ................................................. 816
6.4. ALE Timing Register 0 to 7 (ATIM0 to ATIM7) ............................................................... 819
6.5. SDRAM Mode Register (SDMODE) ............................................................................... 820
6.6. Refresh Timer Register (REFTIM) .................................................................................. 824
6.7. Power Down Count Register (PWRDWN) ...................................................................... 826
6.8. SDRAM Timing Register (SDTIM) .................................................................................. 827
6.9. SDRAM Command Register (SDCMD) .......................................................................... 830
6.10. Memory Controller Register (MEMCERR) .................................................................... 832
6.11. Division Clock Register (DCLKR) ................................................................................. 834
6.12. Error Status Register (EST) .......................................................................................... 836
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