Cypress FM4 Series - Page 192

CHAPTER 6: Low Power Consumption Mode
192 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
Overview of Sleep Modes
Sleep mode is classified as a standby mode. In Sleep mode, the clock supply to the CPU stops. Since the
stop of the clock supply to the CPU causes the CPU to stop, power consumption is reduced. Resources
connected to the AHB bus and the APB bus continue operating.
Below are the five Sleep modes, which are defined according to the master clock being used at the
transition to Sleep mode.
 High speed CR sleep mode
With the high speed CR oscillator clock selected as the master clock, the system transits to high speed
CR sleep mode when a request for transition to Sleep mode is made. The respective states of the PLL
Multiplier Circuit, the main oscillator and the sub oscillator change according to the respective settings of
the PLLE bit, the MOSCE bit and the SOSCE bit, respectively. The low speed CR oscillator is always in
the active state.
 Main sleep mode
With the main clock selected as the master clock, the system transits to main sleep mode when a request
for transition to Sleep mode is made. The respective states of the PLL Multiplier Circuit and the sub
oscillator change according to the respective settings of the PLLE bit and the SOSCE bit, respectively.
The high speed CR oscillator and the low speed CR oscillator are always in the active state.
 PLL sleep mode
With the PLL clock selected as the master clock, the system transits to PLL sleep mode when a request
for transition to Sleep mode is made. The high speed CR oscillator and the low speed CR oscillator are
always in the active state. The respective states of the main oscillator and the sub oscillator change
according to the respective settings of the MOSCE bit and the SOSCE bit, respectively.
 Low speed CR sleep mode
With the low speed CR oscillator clock selected as the master clock, the system transits to low speed CR
sleep mode when a request for transition to Sleep mode is made. The state of the sub oscillator changes
according to the setting of the SOSCE bit. The main oscillator, the high speed CR oscillator and the PLL
Multiplier Circuit cannot be used.
 Sub sleep mode
With the sub-clock selected as the master clock, the system transits to sub-sleep mode when a request
for transition to Sleep mode is made. The The sub oscillator and the low speed CR oscillator are always
in the active state. The main oscillator, the high speed CR oscillator and the PLL Multiplier Circuit cannot
be used.