Contents
20 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
2.45. MMC Response Check Bit Register ............................................................................. 906
2.46. Card Detect Setting Register ........................................................................................ 907
3. MMC Boot Operation ................................................................................................................... 908
3.1. Example of Controlling Alternative Boot Mode (Using ADMA)........................................ 910
4. MMC Wait IRQ ............................................................................................................................ 912
4.1. Example of Controlling Wait IRQ .................................................................................... 912
5. SDCLK ......................................................................................................................................... 914
CHAPTER 16: Debug Interface ............................................................................................................... 915
1. Overview and Configuration ........................................................................................................ 916
2. Pin Description ............................................................................................................................ 917
2.1. Pins for Debug Purposes ................................................................................................ 918
2.2. Trace Pins ...................................................................................................................... 919
2.3. Functions Initially Assigned to Pins ................................................................................ 920
2.4. Internal Pull-Ups of JTAG Pins ....................................................................................... 921
CHAPTER 17: Flash Memory .................................................................................................................. 923
CHAPTER 18: Unique ID Register .......................................................................................................... 925
1. Overview ...................................................................................................................................... 926
2. Registers ..................................................................................................................................... 927
2.1. Unique ID Register 0 (UIDR0: Unique ID Register 0) ..................................................... 928
2.2. Unique ID Register 1 (UIDR1: Unique ID Register 1) ..................................................... 929
CHAPTER 19: Programmable CRC ........................................................................................................ 931
1. Overview of the Programmable CRC........................................................................................... 932
1.1. Overview ........................................................................................................................ 932
2. Configuration and Operation of the Programmable CRC............................................................. 933
2.1. Configuration of the Programmable CRC ....................................................................... 933
2.2. Operation of the Programmable CRC ............................................................................. 934
3. Methods for Controlling the Programmable CRC ........................................................................ 936
3.1. Control Flow for the Programmable CRC (during input data transfer from CPU) ........... 936
3.2. Control Flow for the Programmable CRC (during input data DMA transfer
with DSTC).................................................................................................................. 938
4. Registers of the Programmable CRC .......................................................................................... 940
4.1. Control Register List ....................................................................................................... 940
4.2. CRC Computing Generator Polynomial Register............................................................ 941
4.3. CRC Computing Initial Value Register ............................................................................ 943
4.4. CRC Computing Result XOR Value Register ................................................................. 944
4.5. CRC Computing Configuration Register ......................................................................... 945
4.6. CRC Computing Input Data Register .............................................................................. 949
4.7. CRC Computing Output Data Register ........................................................................... 950
5. Example of the Programmable CRC Computing ......................................................................... 951
5.1. Computing Example 1 .................................................................................................... 951
5.2. Example of Computing 2 ................................................................................................ 953
Appendixes .............................................................................................................................................. 955
A. Register Map ............................................................................................................................... 956
1. Register Map ....................................................................................................................... 958
1.1. FLASH_IF ....................................................................................................................... 959
1.1.1. TYPE1-M4, TYPE2-M4 Products ..................................................................... 959
1.1.2. TYPE3-M4 Product .......................................................................................... 960
To Next Page
Loading...
