CHAPTER 7-2: VBAT Domain(A)
274 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
Initial settings of hibernation operation
Below are the initial settings required for the hibernation operation.
− Alarm setting of the RTC
For the method of setting the alarm, refer to "CHAPTER: RTC Count Block" in FM4 Family
PERIPHERAL MANUAL Timer Part.
− Setting of the P49/VWAKEUP pin
Write "1" to the VPFR1 bit in the VBPFR Register.
− Setting of the P48/VREGCTL pin
Write "1" to the VPFR0 bit in the VBPFR Register.
The CPU core can transit to the hibernation state even when the alarm setting of the RTC and the setting
of the P49/WAKEUP pin are not done.
If the CPU core transits to the hibernation state with both settings not done, it cannot return to the normal
operation state.
Setting of hibernation start
With both alarm interrupt of the RTC and wakeup (P49/VWAKEUP pin) cleared, if 1 is written to bit0 in the
HIBRST Register, the P48/VREGCTL pin becomes 0, the on-board regulator transits to the standby state
and the VCC power supply is turned off.
Judging return from hibernation state and operations after return from hibernation state
If an alarm interrupt of the RTC or a wakeup request occurs, the P48/VREGCTL pin becomes 1, the
on-board regulator returns from the standby state and the VCC power supply is turned on.
If the VCC power supply is turned on, the CPU core executes the normal power-on operation.
To judge whether the CPU core has returned from the hibernation state, check whether the following
three conditions are met.
− The VBAT Domain has been powered on (Power-on bit (PON) in the VDET Register).
− The alarm interrupt of the RTC has occurred (Alarm coincidence flag bit (INTALI) in the WTCR12
Register).
− A wakeup up request has been made (Wakeup request bit (WUP0) in the EWKUP Register).
Notes:
− The P48/VREGCTL pin becomes "0" immediately after 1 has been written to Hibernation start bit
(HIBRST) in the HIBRST Register.
− Complete all operations for turning off the VCC power supply before witting 1 to Hibernation start
bit (HIBRST) in the HIBRST Register.
− In the hibernation operation, the VCC power supply is assumed to be tuned off with the control of
P48/VREGCTL pin.
When the on-board regulator is not directly controlled with P48/VREGCTL pin at debugging, turn
off the VCC power supply once by manual operation.
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