Cypress FM4 Series - Page 312

CHAPTER 7-3: VBAT Domain(B)
312 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
 Allowed transfer combination
Though it should be checked that the TRANS bit in the WTCR0 Register is 0 before the start of a recall
operation or of a save operation, the transfers in a combination with the "o" mark in the following table can
be executed exceptionally.
CREAD
CWRITE
PREAD
PWRITE
BREAD
BWRITE
CREAD



o
o
CWRITE



o
o
PREAD



o
o
PWRITE



o
o
BREAD
o
o
o
o

BWRITE
o
o
o
o

"" indicates that the transfers in that combination can be executed simultaneously.
"" indicates that the transfers in that combination cannot be executed simultaneously.
 Notes on description
In the peripheral manuals of the FM4 Family, a read access and a write access to a register of interface
circuit type 2 or of interface circuit type 3 are defined as follows.
Read access: A recall operation is executed and then data in the buffer is read.
Write access: A recall operation is executed to update the entire buffer. Afterward, the part in the buffer
corresponding to the data of the write access is replaced with such data, and then a save operation is
executed.
 Usage Precautions
− Do not access the buffer during a save operation or a recall operation. It is not possible to identify
whether correct data has been saved while accessing the buffer during a save operation, neither is
it possible to identify whether correct data has been read while accessing the buffer during a recall
operation.
− Set the VB_CLKDIV Register to a value that makes the transfer clock for PREAD, PWRITE,
BREAD and BWRITE generated by dividing PCLK2 become 1 MHz or below.