Cypress FM4 Series - Page 388

CHAPTER 8: Interrupts
388 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
[bit15:8] Reserved: Reserved bits
A reserved bit reads 0.
[bit7:0] SELIRQ[7:0]
The SELIRQ[7:0] bits specify the IRQ no. of a peripheral interrupt to be relocated.
For the IRQ no., see the column of IRQ no. in Table 3-1 and Table 3-2.
Value
Description
11 to 127
IRQ no. of a peripheral interrupt to be relocated
0x00
No peripheral interrupt to be relocated
Value other than
the above
Setting prohibited
Examples of and notes on setting
For instance, the SELIRQ[7:0] bits and the SELBIT[7:0] bits in the IRQ003SEL Register are set to 25 and
0b00000010 respectively. According to these settings, the IRQ no.25 interrupt (MFT unit 0 FRT ch.1 zero
detection interrupt) assigned to bit1 in the IRQ025MON Register is relocated to bit1 in the IRQ003MON
Register. If an MFT unit 0 FRT ch.1 zero detection interrupt is generated, an IRQ no.3 interrupt is
generated and 1 can be read out from bit1 in the IRQ003MON Register. From the original interrupt
position (bit1 in the IRQ025MON Register), no interrupt is generated any more. From bit1 in the
IRQ025MON Register, “0” is always read out.
On the other hand, the IRQ no.25 interrupt (MFT unit 0 FRT ch.0 zero detection interrupt) can still be
received from bit0 in the IRQ025MON Register, to which the interrupt is assigned. Therefore, the two
interrupt sources aggregated by logical OR to bit0 and bit1 in the IRQ025MON Register can be received
from the IRQ003MON Register and the IRQ025MON Register respectively.
The same IRQ no. can be specified in the SELIRQ[7:0] bits in more than one Relocate Interrupt Selection
Register from IRQ003SEL to IRQ010SEL. For instance, in addition to the settings of the IRQ003SEL
Register mentioned above, if the SELIRQ[7:0] bits and the SELBIT[7:0] bits in the IRQ004SEL Register
are set to 25 and 0b00000100 respectively, the IRQ no.25 interrupt (MFT unit 0 FRT ch.2 zero detection
interrupt) assigned to bit2 in the IRQ025MON Register can be received from bit2 in the IRQ004MON
Register. Therefore, the three interrupt sources aggregated by logical OR to bit0, bit1 and bit2 in the
IRQ025MON Register can be received from the IRQ003MON Register, the IRQ004MON Register and
the IRQ025MON Register respectively.
However, one interrupt source cannot be selected for different relocate interrupts. (If the same IRQ no. is
specified in the SELIRQ[7:0] bits in different Relocate Interrupt Selection Registers, their respective
settings of the SELBIT[7:0] bits cannot be the same.)
If more than one bit of the SELBIT[7:0] bits are set to 1, multiple interrupt sources selected are
aggregated by logical OR to become a relocate interrupt.
A bus reset initializes the settings of all Relocate Interrupt Selection Registers (IRQ003SEL to
IRQ010SEL). After the relocate interrupt selection settings in the IRQ003SEL to IRQ010SEL Registers
have been initialized, the IRQ no.3 to IRQ no.10 interrupts are no longer generated.
Before modifying the settings of any of the IRQ003SEL to IRQ010SEL Registers, ensure that no interrupt
signal has been asserted.