CHAPTER 10: DMAC
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 457
Explanation of Block Diagram
DMAC
DMAC is in maximum 8-ch configuration. Each channel performs independent transfer. The priority
controller controls the transfer operations of these channels, when there is a conflict among them.
Connection to the system
The diagram of the system configuration in the figure has been simplified for explanation purposes. For
more details, see the chapter "System Overview". DMAC is connected to CPU, Flash, RAM and
Peripherals via the system bus. It has its own bus that is independent from the CPU bus, allowing for
transfer operation at CPU bus access. It accesses any address area in the system by specifying the
address of transfer destination and transfer source for each channel in order to transfer data between the
memory and Peripheral. Since some areas cannot be accessed from DMAC, check the memory map.
Connection of the hardware transfer request signal
The interrupt signal from the Peripheral supporting hardware transfer is selected in the interrupt controller
block (indicated as DRQSEL in Figure 2-1) either to be used as the interrupt signal to CPU or the DMA
transfer request signal to DMAC.
When performing DMA transfer by hardware request, connect the interrupt signal from each Peripheral as
the transfer request signal to DMAC in advance by setting DRQSEL. The interrupt signal from the
Peripheral that does not support hardware transfer cannot be used as the DMA transfer request signal.
When the interrupt signal is used as the transfer request signal to DMAC, it cannot be used as the
interrupt signal to CPU. See the chapter "Interrupts".
There are 32 DMA transfer request signals to be input to DMAC. For the correspondence between each
signal and Peripheral, see Table 2-1 in the next section.
Interrupt signals from the peripheral that is not integrated cannot be selected. It should be noted that for
a Peripheral with multiple channels and multiple interrupt factors, some interrupts support DMA transfer,
while others don’t.
In the case of hardware transfer, each channel of DMAC selects one transfer request signal out of the
above 32 transfer request signals in its operation. The IS register is used for the selection.
Connection of the hardware transfer request clear signal
Some of the Peripherals that support hardware transfer are required to clear the transfer request signal
(interrupt signal) after the completion of the transfer. Although it is not illustrated in Figure 2-1, the transfer
request signal is cleared for such Peripherals via DMAC by selecting it by DRQSEL.
Connection of the hardware transfer stop request signal
The multifunction serial unit (hereinafter abbreviated as "MFS") outputs the DMA transfer stop request
signal. Although it is not illustrated in Figure 2-1, MFS’s transfer stop request signal is connected to
DMAC, when MFS is selected by DRQSEL. When the transfer stop request signal is asserted, DMAC
stops the transfer operation. It is configured to mask the succeeding transfer request signals.
Conditions that are asserted by MFS's transfer stop request signal show below.
− If received interrupts are enabled (SCR:RIE=1), a received interrupt occurs (SSR:PE bit, FRE bit,
or ORE bit is set to 1).
− If chip select error interrupt are enabled (SACSR:CSEIE=1), a chip select error interrupt occurs
(SACSR:CSE bit is set to 1).
Interrupt signal from DMAC
Although it is not illustrated in Figure 2-1, an interrupt signal used to give notification of transfer
completion is connected to NVIC. Each channel has 8 interrupt outputs.
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