CHAPTER 11: DSTC
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 565
bit[3] DER (Double error)
The DER bit indicates whether a double error has occurred. With the EST[2:0] bits set to a value other
than "000" and the DER bit set to "0", if a new transfer error occurs, the DER bit is set to "1". The DER bit
is cleared to "0" by the ERCLR command.
Writing a value to DESP causes no operation to be executed.
Indicates that no double error has occurred. (Initial value)
Indicates that a double error has occurred.
bit[4] ESTOP (Error stop)
The ESTOP bit indicates that the DSTC is in the error stop state. With CFG:ESTE set to "1", if a transfer
error occurs, the ESTOP bit is set to "1". In the error stop state, the transfer start of the DSTC is held. The
ESTOP bit is cleared to "0" by the ERCLR command. If this bit is cleared to "0", the transfer held starts. If
this bit is "1", a write access to the SWTR Register is ignored.
Writing a value to DESP causes no operation to be executed.
Indicates that the DSTC is not in the error stop state. (Initial value)
Indicates that the DSTC is in the error stop state.
bit[5] Reserved
The read value is indeterminate. The value written to this bit is ignored.
bit[6] EHS (Error hardware software)
The EHS bit indicates whether the DES that has caused an error has been started by the HW Start or by
the SW Start. In the case of EST ≠ 000, even if a new transfer error occurs, DESP keeps details of the
previous transfer error. In the case of EST = 000, the value of DESP is undefined.
Writing a value to this bit does not cause any operation to be executed.
An error has occurred in a transfer started by the SW Start or by the Chain Start in that SW Start.
An error has occurred in a transfer started by the HW Start or by the Chain Start in that HW Start.
bit[7] Reserved
The read value is indeterminate. The value written to this bit is ignored.
bit[15:8] ECH[7:0] (Error hardware channel)
If the EST[2:0] bits are not "000" and the EHS bit is "1", the ECH[7:0] bits indicate the number of the HW
Start channel that has caused an error. In the case of EST ≠ 000, even if a new transfer error occurs, the
ECH[7:0] bits keep the HW Start channel number of the previous transfer error. If the EST[2:0] bits are
"000" or the EHS bit is "0", the value of the ECH[7:0] bits is indeterminate.
Writing a value to these bits does not cause any operation to be executed.
The ECH[7:0] bits indicate the HW channel number if the DES that has caused a transfer error
was started by the HW Start.
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