Cypress FM4 Series - Page 577

CHAPTER 11: DSTC
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 577
Descriptor configuration (in mode 1)
Address: DESTP + DESP + 0x04
bit
31
16
15
8
7
0
Field
ORM[15:0]
IRM[7:0]
IIN[7:0]
C attribute
R/W
R/W
R/W
D attribute
R/W
R/W
R/W
Descriptor function (in mode 1)
bit[7:0] IIN[7:0] (Inner loop initial)
The IIN[15:0] bits specify the initial value of the inner loop counter in the transfer number counter. They
can be set to a value in the range of "1" to "256" inclusive. Setting the IIN[7:0] bits to "0x00" is equivalent
to setting them to "256".
The DSTC does not modify the value of this area during a transfer. If OuterReload of DES1 is enabled,
the DSTC copies the value of DES[7:0] to the IIN[7:0] bits after the final transfer.
bit[15:8] IRM[7:0] (Inner loop remain)
The IRM[7:0] bits specify the remain value of the inner loop counter in the transfer number counter. Set
the IRM[7:0] bits to the same value as the IIN[7:0] bits.
The DSTC decreases the value of the IRM[7:0] bits before writing back it to the DES. The DSTC stores
"0x01" in IRM at the end of a transfer. If OuterReload of DES1 is enabled, the DSTC copies the value of
DES4[15:8] to the IRM[7:0] bits after the final transfer. If the transfer ends in the form of error, the DSTC
stores the value appearing before the end of the transfer, and in turn, it is necessary to initialize the
IRM[7:0] bits via the CPU. If the DSTC detects that the value of the IRM[7:0] bits is larger than the value
of the IIN[7:0] bits, it notifies the system of a DES open error.
bit[31:16] ORM[15:0] (Outer loop remain)
The ORM[15:0] bits specify the remain value of the outer loop counter in the transfer number counter.
They can be set to a value in the range of "1" to "65536" inclusive. Setting the ORM[15:0] bits to "0x0000"
is equivalent to setting them to "65536".
The DSTC decreases the value of the ORM[15:0] bits before writing back it to the DES. The DSTC stores
"0x0001" in the ORM[15:0] bits at the end of a transfer. If OuterReload of DES1 is enabled, the DSTC
copies the value of DES4[31:16] to the IRM[7:0] bits after the final transfer. If the transfer ends in the form
of error, the DSTC stores the value appearing before the end of the transfer, and in turn, it is necessary to
initialize the ORM[15:0] bits via the CPU.
The setting is that DES0.DV[1]=1 and DES1 is need to rebuild (DES1 is not returned to the start value),
caused to notify a DES open error from the DSTC.