Cypress FM4 Series - Page 584

CHAPTER 12: I/O Port
584 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
*2: When one of the followings is set, the input value is fixed to 0.
Otherwise, the pin is set as the digital input pin.
− ADE/SPSR=1
− DAE=1
Notes:
− USB pin does not have pull-up resistor.
− If it does not have a pull-up resistor, the PCR register setting is null.
− PZR register function is implemented only in some specific pins.
− Only pins described as "PZR register control is enabled" in the remarks column of I/O
CIRCUIT TYPE of the Data Sheet can control this feature.
− PFR0[4:0] register is not initialized by deep standby transition reset.
− For details of DAE bit, 5.1. D/A Control Register (DACR) in 12-bit D/A CONVERTER in Analog
Macro Part.
− The register settings of PFR, DDR, PDIR, PDOR, PCR, and PZR registers are invalid for ports
(P49 to P46) in VBAT Domain. These bits have the same configuration as I/O Ports, but they are
set with VBAT Registers (VBPFR, VBDDR, VBDIR, VBDOR, and VBPZR). For details on
registers, see Chapter “VBAT Domain”.
Table 2-1 describes register function.
− The PFR, DDR, PDIR, PDOR, and PCR register have 1-bit control register for each I/O port and
select a function for the I/O port.
− The ADE register has 1-bit control register for each I/O port which doubles as an analog input pin
and selects a function for the I/O port.
− The SPSR register selects a function for the I/O port which doubles as a USB pin or an oscillation
pin.
− The EPFR register has control register for each I/O pin of peripheral functions and selects to which
I/O port an I/O pin of peripheral functions will be relocated.
− PZR register sets open drain control in pseudo mode by the Hi-Zing I/O port when outputting the
High level of a particular pin.
− PDSR register selects drive capability of particular functions.