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Cypress FM4 Series - Page 597

Cypress FM4 Series
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CHAPTER 12: I/O Port
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 597
Notes:
The "x" of PFRx is a wildcard. PFRx indicates PFR0, PFR1, PFR2, etc.
The "x" of Px0 and PxF is a wildcard. Px0 indicates P00, P10, P20, etc. PxF indicates P0F, P1F,
P2F, etc.
Functions can be set for 16 ports from PxF to Px0.
Each bit in the register sets each pin individually. There is a one-to-one correspondence between
bit assignment and the order of pins. For example, bit15 of PFR0 sets P0F, bit14 of PFR0 sets
P0E, and bit0 of PFR0 sets P00.
As a JTAG pin is selected for P04 to P00, the initial value is 1.
For a pin which is not available in your product, must write initial value to the bit, and the read
value is undefined.
For GPIO pin sharing with oscillating pins(X0, X1), writing “PFR=1” is prohibited. To use the pin
as oscillating pin, be sure to set “PFR=0”.
The setting of P46 to P49 with this register is invalid. Use VbatIO port function control register
(VBPFR) of VBAT RTC to set these pins. For details of VBAT RTC, see VBAT Domain.
PFR0[4:0] register is not initialized by deep standby transition reset.
In TYPE3-M4 products, the PFRx's bit which is corresponded to the pin assigned of HDMI-CEC,
when CECR0B/CECR1B of EPFR18 is not "0b00",the bit is not initialized by deep standby
transition reset.

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