Cypress FM4 Series - Page 655

CHAPTER 12: I/O Port
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 655
Notes:
− I/O selection of the external bus data[15:8] can be controlled collectively with EPFR10.bit1.
I/O selection of the external bus data[15:8] can be controlled by each bit also with
EPFR11.bit[24:17].
EPFR10.bit1 setting has the higher priority than EPFR11.bit[24:17] setting.
To control I/O selection by setting EPFR11.bit[24:17], it is necessary to set EPFR10.bit1=0.
− I/O selection of the external bus address[7:1], MCSX0, and external bus data[7:0] can be
controlled collectively with EPFR10.bit0.
I/O selection of the external bus address[7:1], MCSX0, and external bus data[7:0] can be
controlled by each bit also with EPFR11.bit[16:1].
EPFR10.bit0 setting has the higher priority than EPFR11.bit[16:1] setting.
To control I/O selection by setting EPFR11.bit[16:1], it is necessary to set EPFR10.bit0=0.
− This register is not initialized by deep standby transition reset.