Cypress FM4 Series - Page 719

CHAPTER 12: I/O Port
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 719
[bit7:6] PNL_PD3E: PNL_PD3 Output Select bits
Selects output for PNL_PD3.
bit
Description
Reading
Reads out the register value.
Writing
00
Does not produce output of GDC Panel PNL_PD3. [Initial value]
01
Uses PNL_PD3_0 at the output pin of GDC Panel PNL_PD3.
10
Setting is prohibited.
11
Setting is prohibited.
[bit5:4] PNL_PD2E: PNL_PD2 Output Select bits
Selects output for PNL_PD2.
bit
Description
Reading
Reads out the register value.
Writing
00
Does not produce output of GDC Panel PNL_PD2. [Initial value]
01
Uses PNL_PD2_0 at the output pin of GDC Panel PNL_PD2.
10
Setting is prohibited.
11
Setting is prohibited.
[bit3:2] PNL_PD1E: PNL_PD1 Output Select bits
Selects output for PNL_PD1.
bit
Description
Reading
Reads out the register value.
Writing
00
Does not produce output of GDC Panel PNL_PD1. [Initial value]
01
Uses PNL_PD1_0 at the output pin of GDC Panel PNL_PD1.
10
Setting is prohibited.
11
Setting is prohibited.
[bit1:0] PNL_PD0E: PNL_PD0 Output Select bits
Selects output for PNL_PD0.
bit
Description
Reading
Reads out the register value.
Writing
00
Does not produce output of GDC Panel PNL_PD0. [Initial value]
01
Uses PNL_PD0_0 at the output pin of GDC Panel PNL_PD0.
10
Setting is prohibited.
11
Setting is prohibited.
Notes:
− This register does not exist in TYPE1-M4, TYPE2-M4, TYPE3-M4, TYPE5-M4, TYPE6-M4
products.
− This register is not initialized by deep standby transition reset.