EasyManua.ls Logo

Cypress FM4 Series - Page 735

Cypress FM4 Series
1102 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
CHAPTER 12: I/O Port
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 735
[bit3:2] MAINXC: Main Clock (Oscillation) Pin Setting Register
These bits set a pin as a main clock (oscillation) pin.
bit
Description
Reading
Reads out the register value.
Writing
00
Does not use two pins of X0 and X1 as main clock (oscillation) pins but as digital input/output
pins.
01
Uses two pins of X0 and X1 as main clock (oscillation) pins. [Initial value]
(An I/O cell will be in a state of input direction, input cut-off, and pull-up disconnection.)
10
Setting is prohibited.
11
Uses X0 pin as an external clock input pin.
Uses X1 pin as a digital input/output.
[bit1:0] SUBXC: Sub Clock (Oscillation) Pin Setting Register
These bits exist in TYPE5-M4 products.
These bits set a pin as a sub clock (oscillation) pin.
bit
Description
Reading
Reads out the register value.
Writing
00
Does not use two pins of X0A and X1A as sub clock (oscillation) pins but as digital
input/output pins.
01
Uses two pins of X0A and X1A as sub clock (oscillation) pins. [Initial value]
(An I/O cell will be in a state of input direction, input cut-off, and pull-up disconnection.)
10
Setting is prohibited.
11
Uses X0A pin as an external clock input pin.
Uses X1A pin as a digital input/output.
These bits do not exist in products other than TYPE5-M4.
0b01 is read from these bits.
When writing these bits, set them to 0b01.
Notes:
Only writing 01 to the MAINXC bit does not make a main clock start oscillation.
To start oscillation, enable oscillation by the MOSCE bit of the System Clock Mode Control
Register (SCM_CTL), which is described in the chapter Clock, after writing 01 to the MAINXC bit.
In TYPE5-M4 products, only writing 01 to the SUBXC bit does not make a sub clock start
oscillation. To start oscillation, enable oscillation by the SOSCE bit of the System Clock Mode
Control Register (SCM_CTL), which is described in the chapter Clock, after writing 01 to the
SUBXC bit.
In the products other than TYPE5-M4, for procedures of enabling the oscillation of sub-clock, see
Chapter Clock.
This register is not initialized by deep standby transition reset.

Table of Contents

Related product manuals