CHAPTER 12: I/O Port
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 737
Notes:
− The "x" description of PZRx is wildcard. It shows PZR0, PZR1, PZR2, and so on.
− The function of the PZR register is implemented only in some specific pins.
Only pins described as "PZR register control is enabled" in remarks column of I/O circuit type of
Data Sheet can control open drain.
− PZR register does not exist in all pins. However, even the pins that do not have PZR registers
can control pseudo open drain by the setting of DDR register if they are used as GPIO.
In such a case, after setting PFR = 0 (GPIO setting) and PDOR = 0,
When setting L output: used as DDR = 1 (output direction).
When setting Hi-Z output: used as DDR = 0 (input direction).
However, in open drain by the GPIO setting, you cannot apply voltage that exceeds VCC at Hi-Z.
− The settings of P49 to P46 with this register are prohibited. The settings should be made with
VBAT Port Pseud Open Drain Setting Register(VBPZR). For details on VBAT, see VBAT Domain.
− This register is not initialized by deep standby transition reset.
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