CHAPTER 15: SD Card Interface
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 911
(1) Prepare the ADMA descriptor table in the system memory.
(2) Set the descriptor address of the ADMA in the ADMA System Address Register.
(3) Set the Boot Mode Enable for MMC bit in the MMC/eSD Control Register to 0.
In addition, to enable boot acknowledge reception, set the Boot Ack Enable for MMC bit to 1; to complete
the boot operation automatically according to the end attribute in the ADMA descriptor table, set the boot
auto abort enable for MMC bit to 1.
Moreover, if a boot operation is executed with the Boot Auto Abort Enable for MMC bit set to 0, the data
transfer becomes an infinite block read transfer. To end the transfer, send CMD0 (Reset) as described
below.
Procedure for sending CMD0 (Reset)
− Check that the Command Inhibit (CMD) bit in the Present State Register is 0.
− Set the Argument 1 Register to 0.
− Set the following bits in the Command Register as follows: the Response Type Select bits to 0b00
(No Response), the Data Select bit to 0 (No Data Present), the Command Type to 0b11 (Abort) and
the Command Index bit to 0.
A write access to the upper bits in the Command Register causes CMD0 (Reset) set above to be sent.
(4) Set the Data Timeout Counter Value bits to the biggest value among tBA, tBD and NAC of timing
specifications.
(5) Set the DMA Select bits to "0b10" (32-bit address ADMA2 is selected).
Set the Extended Data Transfer Width and the Data Transfer Width bit according to the type of
communication.
In addition, this macro does not use the High Speed Enable bit in transfer control. (The High Speed
Enable bit in this macro is meaningless.)
(6) Set to 0xFFFFFFFA.
(7) Set the Multi / Single Block Select bit to 1 (Multiple Block).
Set the Data Transfer Direction Select bit to 1 (Read).
Set the Auto Command Enable bits to 0b00 (Auto Command Disabled).
Set the Block Count Enable bit to 0 (Disable).
Set the DMA Enable bit to 1 (DMA Data transfer).
(8) Set the Response Type Select bits to 0b00 (No Response).
Set the Data Present Select bit to 1 (Data Present).
Set the Command Type bits to 0b00 (Normal).
Set the Command Index bits to 0. A write access to the upper bits in the Command Register causes the
boot operation to start.
(9) Wait for the Command Complete Interrupt.
(10) Clear the Command Complete Interrupt Status bit to 0.
(11) Wait for the interrupt to determine whether the boot operation has been completed.
If the ADMA Error Interrupt, the Data Error Interrupt or the Boot Acknowledge Error Interrupt is generated,
proceed to (13).
If no error interrupt is generated, but the Transfer Complete Interrupt is generated, proceed to (12).
(12) Clear the Transfer Complete Interrupt Status bit to 0.
(13) Clear the error interrupt status bit corresponding to the interrupt generated to 0.
(14) Send CMD0 (Reset) and abort the boot operation. After aborting the boot operation, execute a
software reset.
See (3) for the procedure for sending CMD0 (Reset).
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