CHAPTER 15: SD Card Interface
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 913
(1) Set the Wait IRQ Enable bit in the MMC Wait IRQ Control Register to 1 (Enable).
(2) Set the argument of CMD40 (Wait IRQ).
(3) Set the Response Type Select bits to 0b10 (Response Length 48).
Set the Command CRC Check Enable bit to 1 (Enable).
Set the Command Index Check Enable bit to 1 (Enable).
Set the Data Present Select bit to 0 (No Data Present).
Set the Command Type bits to 0b00 (Normal).
Set the Command Index bits to 40.
A write access to the upper bits in the Command Register causes the sending of CMD0 (Reset) to start.
(4) Wait for the Command Complete Interrupt, or for the cancellation of CMD40 by the Host Driver.
(5) Check whether the Command Complete Interrupt, the Command Index Error Interrupt, the Command
End Bit Error Interrupt, the Command CRC Error Interrupt or the Command Timeout Error Interrupt has
been generated.
If any of the Command Index Error, the Command End Bit Error Interrupt, the Command CRC Error
Interrupt and the Command Timeout Error Interrupt has been generated, proceed to (7).
If none of the Command Index Error, the Command End Bit Error Interrupt, the Command CRC Error
Interrupt and the Command Timeout Error Interrupt has been generated, but the Command Complete
has been generated, proceed to (6).
(6) Check the response content of CMD40.
(7) Clear the interrupt status bit corresponding to the interrupt generated to 0.
(8) Start the cancellation of CMD40 by the Host Driver. Read the MMC Wait IRQ Control Register.
(9) Check the value of the Wait IRQ State bit in the MMC Wait IRQ Control Register.
The response of CMD40 can be sent from this macro only when the Wait IRQ State bit is 1.
If the Wait IRQ State bit is 1, proceed to (10) to send the response of CMD40.
The Wait IRQ State bit reading 0 means that either the sending of the CMD40 command has not been
completed, or the response of CMD40 has been received. If the sending of the CMD40 command has not
been completed (The Command Complete Interrupt has not been generated and the Wait IRQ State bit is
0, return to (8).
While checking the value of the Wait IRQ State bit, if the Command Complete Interrupt is generated due
to the reception of the response of CMD40, abort the cancellation of the Wait IRQ and proceed to (5).
(10) Set the content of the response of CMD40 in the Wait IRQ Cancel Response bits in the MMC Wait IRQ
Control Register.
Upon a write access to the Wait IRQ Cancel Response bits at the address 0x12F, output the content set
in the Wait IRQ Cancel Response bits to the CMD line. In addition, the SD card interface receives output
data as the response of CMD40.
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