Table 28-73. Long sample time adder (LSTAdder)
CFG1[ADLSMP] CFG2[ADLSTS]
Long sample time adder
(LSTAdder)
0 xx 0 ADCK cycles
1 00 20 ADCK cycles
1 01 12 ADCK cycles
1 10 6 ADCK cycles
1 11 2 ADCK cycles
Table 28-74. High-speed conversion time adder (HSCAdder)
CFG2[ADHSC] High-speed conversion time adder (HSCAdder)
0 0 ADCK cycles
1 2 ADCK cycles
Note
The ADCK frequency must be between f
ADCK
minimum and
f
ADCK
maximum to meet ADC specifications.
28.4.4.6 Conversion time examples
The following examples use the Figure 28-62, and the information provided in Table
28-70 through Table 28-74.
28.4.4.6.1 Typical conversion time configuration
A typical configuration for ADC conversion is:
• 10-bit mode, with the bus clock selected as the input clock source
• The input clock divide-by-1 ratio selected
• Bus frequency of 8 MHz
• Long sample time disabled
• High-speed conversion disabled
The conversion time for a single conversion is calculated by using the Figure 28-62, and
the information provided in Table 28-70 through Table 28-74. The table below lists the
variables of Figure 28-62.
Table 28-75. Typical conversion time
Variable Time
SFCAdder 5 ADCK cycles + 5 bus clock cycles
Table continues on the next page...
Functional description
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
490 Freescale Semiconductor, Inc.
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