multiplication factor from 640 to 1280. To return the MCGOUTCLK frequency
to 20 MHz, set C4[DRST_DRS] bits to 2'b00 again, and the FLL multiplication
factor will switch back to 640.
C1 = 0x10
C2 = 0x00
C2 = 0x1C
CHECK
CHECK
CHECK
S[OSCINIT] = 1 ?
CONTINUE
IN FEE MODE
NO
NO
NO
YES
YES
YES
START
IN BLPI MODE
S[IREFST] = 0?
S[CLKST] = %00?
Figure 24-19. Flowchart of BLPI to FEE mode transition using an 4 MHz crystal
Chapter 24 Multipurpose Clock Generator (MCG)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 403
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