31.3.1 Status and Control (TPMx_SC)
SC contains the overflow status flag and control bits used to configure the interrupt
enable, module configuration and prescaler factor. These controls relate to all channels
within this module.
Address: Base address + 0h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
DMA
TOF
TOIE
CPWMS
CMOD PS
W
w1c
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TPMx_SC field descriptions
Field Description
31–9
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
8
DMA
DMA Enable
Enables DMA transfers for the overflow flag.
0 Disables DMA transfers.
1 Enables DMA transfers.
7
TOF
Timer Overflow Flag
Set by hardware when the LPTPM counter equals the value in the MOD register and increments. The TOF
bit is cleared by writing a 1 to TOF bit. Writing a 0 to TOF has no effect.
If another LPTPM overflow occurs between the flag setting and the flag clearing, the write operation has
no effect; therefore, TOF remains set indicating another overflow has occurred. In this case a TOF
interrupt request is not lost due to a delay in clearing the previous TOF.
Table continues on the next page...
Memory Map and Register Definition
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
552 Freescale Semiconductor, Inc.
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