NXP Semiconductors KL25 Series - KL25 Sub-Family Reference Manual, Rev. 3, September

ADCx_CLP4 field descriptions
Field Description
31–10
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
9–0
CLP4
Calibration Value
28.3.14 ADC Plus-Side General Calibration Value Register
(ADCx_CLP3)
For more information, see CLPD register description.
Address: 4003_B000h base + 40h offset = 4003_B040h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
CLP3
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
ADCx_CLP3 field descriptions
Field Description
31–9
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
8–0
CLP3
Calibration Value
28.3.15 ADC Plus-Side General Calibration Value Register
(ADCx_CLP2)
For more information, see CLPD register description.
Address: 4003_B000h base + 44h offset = 4003_B044h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
CLP2
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
ADCx_CLP2 field descriptions
Field Description
31–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
7–0
CLP2
Calibration Value
Chapter 28 Analog-to-Digital Converter (ADC)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 477