NXP Semiconductors KL25 Series - System Clock Gating Control Register 5 (SIM_SCGC5)

12.2.9 System Clock Gating Control Register 5 (SIM_SCGC5)
Address: 4004_7000h base + 1038h offset = 4004_8038h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0 0 0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
PORTE
PORTD PORTC
PORTB PORTA
1 0
TSI
0 0
LPTMR
W
Reset
0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0
SIM_SCGC5 field descriptions
Field Description
31–20
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
19
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
18–14
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
13
PORTE
Port E Clock Gate Control
This bit controls the clock gate to the Port E module.
0 Clock disabled
1 Clock enabled
12
PORTD
Port D Clock Gate Control
This bit controls the clock gate to the Port D module.
0 Clock disabled
1 Clock enabled
11
PORTC
Port C Clock Gate Control
This bit controls the clock gate to the Port C module.
0 Clock disabled
1 Clock enabled
10
PORTB
Port B Clock Gate Control
This bit controls the clock gate to the Port B module.
Table continues on the next page...
Memory map and register definition
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
206 Freescale Semiconductor, Inc.