NXP Semiconductors KL25 Series - Chapter 40; UART Baud Rate Register: High (Uartx_Bdh)

40.2.1 UART Baud Rate Register: High (UARTx_BDH)
This register, along with UART_BDL, controls the prescale divisor for UART baud rate
generation. To update the 13-bit baud rate setting [SBR12:SBR0], first write to
UART_BDH to buffer the high half of the new value and then write to UART_BDL. The
working value in UART_BDH does not change until UART_BDL is written.
Address: Base address + h offset
Bit 7 6 5 4 3 2 1 0
Read
LBKDIE RXEDGIE SBNS SBR
Write
Reset
0 0 0 0 0 0 0 0
UARTx_BDH field descriptions
Field Description
7
LBKDIE
LIN Break Detect Interrupt Enable (for LBKDIF)
0 Hardware interrupts from UART_S2[LBKDIF] disabled (use polling).
1 Hardware interrupt requested when UART_S2[LBKDIF] flag is 1.
6
RXEDGIE
RxD Input Active Edge Interrupt Enable (for RXEDGIF)
0 Hardware interrupts from UART_S2[RXEDGIF] disabled (use polling).
1 Hardware interrupt requested when UART_S2[RXEDGIF] flag is 1.
5
SBNS
Stop Bit Number Select
SBNS determines whether data characters are one or two stop bits.
0 One stop bit.
1 Two stop bit.
4–0
SBR
Baud Rate Modulo Divisor.
The 13 bits in SBR[12:0] are referred to collectively as BR, and they set the modulo divide rate for the
UART baud rate generator. When BR is cleared, the UART baud rate generator is disabled to reduce
supply current. When BR is 1 - 8191, the UART baud rate equals BUSCLK/(16×BR).
40.2.2 UART Baud Rate Register: Low (UARTx_BDL)
This register, along with UART_BDH, control the prescale divisor for UART baud rate
generation. To update the 13-bit baud rate setting [SBR12:SBR0], first write to
UART_BDH to buffer the high half of the new value and then write to UART_BDL. The
working value in UART_BDH does not change until UART_BDL is written.
Chapter 40 Universal Asynchronous Receiver/Transmitter (UART1 and UART2)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 751