NXP Semiconductors KL25 Series - UART Status Register 2 (Uartx

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UARTx_S1 field descriptions (continued)

Field Description

all 1s, these bit times and the stop bits time count toward the full character time of logic high, 10 or 11 bit

times depending on the M control bit, needed for the receiver to detect an idle line. When ILT is set, the

receiver doesn't start counting idle bit times until after the stop bits. The stop bits and any logic high bit

times at the end of the previous character do not count toward the full character time of logic high needed

for the receiver to detect an idle line.

To clear IDLE, read UART_S1 with IDLE set and then read the UART data register (UART_D). After IDLE

has been cleared, it cannot become set again until after a new character has been received and RDRF

has been set. IDLE is set only once even if the receive line remains idle for an extended period.

0 No idle line detected.

1 Idle line was detected.

Receiver Overrun Flag

OR is set when a new serial character is ready to be transferred to the receive data register (buffer), but

the previously received character has not been read from UART_D yet. In this case, the new character,

and all associated error information, is lost because there is no room to move it into UART_D. To clear

OR, read UART_S1 with OR set and then read the UART data register (UART_D).

0 No overrun.

1 Receive overrun (new UART data lost).

Noise Flag

The advanced sampling technique used in the receiver takes seven samples during the start bit and three

samples in each data bit and the stop bits. If any of these samples disagrees with the rest of the samples

within any bit time in the frame, the flag NF is set at the same time as RDRF is set for the character. To

clear NF, read UART_S1 and then read the UART data register (UART_D).

0 No noise detected.

1 Noise detected in the received character in UART_D.

Framing Error Flag

FE is set at the same time as RDRF when the receiver detects a logic 0 where the stop bits was expected.

This suggests the receiver was not properly aligned to a character frame. To clear FE, read UART_S1

with FE set and then read the UART data register (UART_D).

0 No framing error detected. This does not guarantee the framing is correct.

1 Framing error.

Parity Error Flag

PF is set at the same time as RDRF when parity is enabled (PE = 1) and the parity bit in the received

character does not agree with the expected parity value. To clear PF, read UART_S1 and then read the

UART data register (UART_D).

0 No parity error.

1 Parity error.

40.2.6 UART Status Register 2 (UARTx_S2)

This register contains one read-only status flag.

KL25 Sub-Family Reference Manual, Rev. 3, September 2012

756 Freescale Semiconductor, Inc.

NXP Semiconductors KL25 Series - UART Status Register 2 (Uartx_S2)