NXP Semiconductors KL25 Series - Interrupt Status Register (Usbx_Istat)

USBx_OTGCTL field descriptions (continued)
Field Description
0 If USB_EN is 1 and HOST_MODE is 0 in the Control Register (CTL), then the D+ Data Line pull-up
resistors are enabled. If HOST_MODE is 1 the D+ and D– Data Line pull-down resistors are engaged.
1 The pull-up and pull-down controls in this register are used.
1–0
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
35.4.9 Interrupt Status register (USBx_ISTAT)
Contains fields for each of the interrupt sources within the USB Module. Each of these
fields are qualified with their respective interrupt enable bits. All fields of this register are
logically OR'd together along with the OTG Interrupt Status Register (OTGSTAT) to
form a single interrupt source for the processor's interrupt controller. After an interrupt
bit has been set it may only be cleared by writing a one to the respective interrupt bit.
This register contains the value of 0x00 after a reset.
Address: 4007_2000h base + 80h offset = 4007_2080h
Bit 7 6 5 4 3 2 1 0
Read STALL ATTACH RESUME SLEEP TOKDNE SOFTOK ERROR USBRST
Write w1c w1c w1c w1c w1c w1c w1c w1c
Reset
0 0 0 0 0 0 0 0
USBx_ISTAT field descriptions
Field Description
7
STALL
Stall Interrupt
In Target mode this bit is asserted when a STALL handshake is sent by the SIE.
In Host mode this bit is set when the USB Module detects a STALL acknowledge during the handshake
phase of a USB transaction.This interrupt can be used to determine whether the last USB transaction was
completed successfully or stalled.
6
ATTACH
Attach Interrupt
This bit is set when the USB Module detects an attach of a USB device. This signal is only valid if
HOSTMODEEN is true. This interrupt signifies that a peripheral is now present and must be configured.
5
RESUME
This bit is set depending upon the DP/DM signals, and can be used to signal remote wake-up signaling on
the USB bus. When not in suspend mode this interrupt must be disabled.
4
SLEEP
This bit is set when the USB Module detects a constant idle on the USB bus for 3 ms. The sleep timer is
reset by activity on the USB bus.
3
TOKDNE
This bit is set when the current token being processed has completed. The processor must immediately
read the STATUS (STAT) register to determine the EndPoint and BD used for this token. Clearing this bit
(by writing a one) causes STAT to be cleared or the STAT holding register to be loaded into the STAT
register.
2
SOFTOK
This bit is set when the USB Module receives a Start Of Frame (SOF) token.
Table continues on the next page...
Chapter 35 Universal Serial Bus OTG Controller (USBOTG)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 629