Table 3-49. Ports Summary (continued)
Feature Port A Port B Port C Port D Port E
Slew Rate Enable
at reset
PTA3/PTA14/
PTA15/PTA16/
PTA17=Disabled;
Others=Enabled
PTB10/PTB11/
PTB16/PTB17 =
Disabled;
Others=Enabled
PTC3/PTC4/PTC5/
PTC6/
PTC7=Disabled;
Others=Enabled
PTD4/PTD5/PTD6/
PTD7=Disabled;
Others=Enabled
PTE16/PTE17/
PTE18/
PTE19=Disabled;
Others=Enabled
Passive Filter
Enable control
PTA4 and
RESET_b only
No No No No
Passive Filter
Enable at reset
RESET_b=Enabled
; Others=Disabled
Disabled Disabled Disabled Disabled
Open Drain Enable
control
1
No No No No No
Open Drain Enable
at reset
Disabled Disabled Disabled Disabled Disabled
Drive Strength
Enable control
No PTB0/PTB1 only No PTD6/PTD7 only No
Drive Strength
Enable at reset
Disabled Disabled Disabled Disabled Disabled
Pin Mux control Yes Yes Yes Yes Yes
Pin Mux at reset PTA0/PTA3/
PTA4=ALT7;
Others=ALT0
ALT0 ALT0 ALT0 ALT0
Lock Bit No No No No No
Interrupt and DMA
Request
Yes No No Yes No
Digital Glitch Filter No No No No No
1. UART signals can be configured for open-drain using SIM_SOPT5 register. IIC signals are automatically enabled for open
drain when selected.
3.10.1.3 GPIO accessibility in the memory map
The GPIO is multi-ported and can be accessed directly by the core with zero wait states at
base address 0xF800_0000. It can also be accessed by the core and DMA masters
through the cross bar/AIPS interface at 0x400F_F000 and at an aliased slot (15) at
address 0x4000_F000. All BME operations to the GPIO space can be accomplished
referencing the aliased slot (15) at address 0x4000_F000. Only some of the BME
operations can be accomplished referencing GPIO at address 0x400F_F000.
3.10.2 TSI Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Chapter 3 Chip Configuration
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 101
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