PMC_LVDSC1 field descriptions (continued)
Field Description
4
LVDRE
Low-Voltage Detect Reset Enable
This write-once bit enables LVDF events to generate a hardware reset. Additional writes are ignored.
0 LVDF does not generate hardware resets
1 Force an MCU reset when LVDF = 1
3–2
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
1–0
LVDV
Low-Voltage Detect Voltage Select
Selects the LVD trip point voltage (V
LVD
).
00 Low trip point selected (V
LVD
= V
LVDL
)
01 High trip point selected (V
LVD
= V
LVDH
)
10 Reserved
11 Reserved
14.5.2 Low Voltage Detect Status And Control 2 register
(PMC_LVDSC2)
This register contains status and control bits to support the low voltage warning function.
While the device is in the very low power or low leakage modes, the LVD system is
disabled regardless of LVDSC2 settings.
See the device's data sheet for the exact LVD trip voltages.
NOTE
The LVW trip voltages depend on LVWV and LVDV bits.
NOTE
The LVWV bits are reset solely on a POR Only event. The
register's other bits are reset on Chip Reset Not VLLS. For
more information about these reset types, refer to the Reset
section details.
Address: 4007_D000h base + 1h offset = 4007_D001h
Bit 7 6 5 4 3 2 1 0
Read LVWF 0
LVWIE
0
LVWV
Write LVWACK
Reset
0 0 0 0 0 0 0 0
Chapter 14 Power Management Controller (PMC)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 241
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