NXP Semiconductors KL25 Series - Power Mode Status Register (SMC_PMSTAT)

SMC_STOPCTRL field descriptions (continued)
Field Description
clocks are gated allowing peripherals running on bus clock to remain fully functional. In PSTOP1, both
system and bus clocks are gated.
00 STOP - Normal Stop mode
01 PSTOP1 - Partial Stop with both system and bus clocks disabled
10 PSTOP2 - Partial Stop with system clock disabled and bus clock enabled
11 Reserved
5
PORPO
POR Power Option
This bit controls whether the POR detect circuit is enabled in VLLS0 mode.
0 POR detect circuit is enabled in VLLS0
1 POR detect circuit is disabled in VLLS0
4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
2–0
VLLSM
VLLS Mode Control.
This field controls which VLLS sub-mode to enter if STOPM=VLLS.
000 VLLS0
001 VLLS1
010
Reserved
011 VLLS3
100 Reserved
101 Reserved
110 Reserved
111 Reserved
13.3.4 Power Mode Status register (SMC_PMSTAT)
PMSTAT is a read-only, one-hot register which indicates the current power mode of the
system.
NOTE
This register is reset on Chip POR not VLLS and by reset types
that trigger Chip POR not VLLS. It is unaffected by reset types
that do not trigger Chip POR not VLLS. See the Reset section
details for more information.
Chapter 13 System Mode Controller (SMC)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 223