40.3.6 Additional UART functions
The following sections describe additional UART functions.
40.3.6.1 8- and 9-bit data modes
The UART system, transmitter and receiver, can be configured to operate in 9-bit data
mode by setting the UART_C1[M]. In 9-bit mode, there is a ninth data bit to the left of
the msb of the UART data register. For the transmit data buffer, this bit is stored in T8 in
UART_C3. For the receiver, the ninth bit is held in UART_C3[R8].
For coherent writes to the transmit data buffer, write to the UART_C3[T8] bit before
writing to UART_D.
If the bit value to be transmitted as the ninth bit of a new character is the same as for the
previous character, it is not necessary to write to UART_C3[T8] again. When data is
transferred from the transmit data buffer to the transmit shifter, the value in
UART_C3[T8] is copied at the same time data is transferred from UART_D to the
shifter.
The 9-bit data mode is typically used with parity to allow eight bits of data plus the parity
in the ninth bit, or it is used with address-mark wakeup so the ninth data bit can serve as
the wakeup bit. In custom protocols, the ninth bit can also serve as a software-controlled
marker.
40.3.6.2 Stop mode operation
During all stop modes, clocks to the UART module are halted.
No UART module registers are affected in stop3 mode.
Because the clocks are halted, the UART module resumes operation upon exit from stop,
only in stop and VLPS mode. Software must ensure stop mode is not entered while there
is a character being transmitted out of or received into the UART module.
40.3.6.3 Loop mode
When UART_C1[LOOPS] is set, the UART_C1[RSRC] bit in the same register chooses
between loop mode (UART_C1[RSRC] = 0) or single-wire mode (UART_C1[RSRC] =
1). Loop mode is sometimes used to check software, independent of connections in the
Chapter 40 Universal Asynchronous Receiver/Transmitter (UART1 and UART2)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 769
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