cleared, UART_BDH[SBNS] is also cleared, selecting the normal 8-bit data mode. In 8-
bit data mode, the shift register holds a start bit, eight data bits, and a stop bit. When the
transmit shift register is available for a new UART character, the value waiting in the
transmit data register is transferred to the shift register, synchronized with the baud rate
clock, and the transmit data register empty (UART_S1[TDRE]) status flag is set to
indicate another character may be written to the transmit data buffer at UART_D.
If no new character is waiting in the transmit data buffer after a stop bit is shifted out the
TxD pin, the transmitter sets the transmit complete flag and enters an idle mode, with
TxD high, waiting for more characters to transmit.
Writing 0 to UART_C2[TE] does not immediately release the pin to be a general-purpose
I/O pin. Any transmit activity in progress must first be completed. This includes data
characters in progress, queued idle characters, and queued break characters.
40.3.2.1 Send break and queued idle
The UART_C2[SBK] bit sends break characters originally used to gain the attention of
old teletype receivers. Break characters are a full character time of logic 0, 10 bit times
including the start and stop bits. A longer break of 13 bit times can be enabled by setting
UART_S2[BRK13]. Normally, a program would wait for UART_S1[TDRE] to become
set to indicate the last character of a message has moved to the transmit shifter, write 1,
and then write 0 to the UART_C2[SBK] bit. This action queues a break character to be
sent as soon as the shifter is available. If UART_C2[SBK] remains 1 when the queued
break moves into the shifter, synchronized to the baud rate clock, an additional break
character is queued. If the receiving device is another Freescale Semiconductor UART,
the break characters are received as 0s in all eight data bits and a framing error
(UART_S1[FE] = 1) occurs.
When idle-line wakeup is used, a full character time of idle (logic 1) is needed between
messages to wake up any sleeping receivers. Normally, a program would wait for
UART_S1[TDRE] to become set to indicate the last character of a message has moved to
the transmit shifter, then write 0 and then write 1 to the UART_C2[TE] bit. This action
queues an idle character to be sent as soon as the shifter is available. As long as the
character in the shifter does not finish while UART_C2[TE] is cleared, the UART
transmitter never actually releases control of the TxD pin. If there is a possibility of the
shifter finishing while UART_C2[TE] is cleared, set the general-purpose I/O controls so
the pin shared with TxD is an output driving a logic 1. This ensures that the TxD line
looks like a normal idle line even if the UART loses control of the port pin between
writing 0 and then 1 to UART_C2[TE].
Chapter 40 Universal Asynchronous Receiver/Transmitter (UART1 and UART2)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 763
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