NXP Semiconductors KL25 Series - UART Control Register 3 (Uartx_C3)

UARTx_S2 field descriptions (continued)
Field Description
BRK13 selects a longer transmitted break character length. Detection of a framing error is not affected by
the state of this bit.
0 Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS =
0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1).
1 Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS =
0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1).
1
LBKDE
LIN Break Detection Enable
LBKDE selects a longer break character detection length. While LBKDE is set, framing error (FE) and
receive data register full (RDRF) flags are prevented from setting.
0 Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M
= 0, SBNS = 1) or 12 (if M = 1, SBNS = 1).
1 Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or
M = 0, SBNS = 1) or 13 (if M = 1, SBNS = 1).
0
RAF
Receiver Active Flag
RAF is set when the UART receiver detects the beginning of a valid start bit, and RAF is cleared
automatically when the receiver detects an idle line. This status flag can be used to check whether an
UART character is being received before instructing the MCU to go to stop mode.
0 UART receiver idle waiting for a start bit.
1 UART receiver active (RxD input not idle).
40.2.7 UART Control Register 3 (UARTx_C3)
Address: Base address + h offset
Bit 7 6 5 4 3 2 1 0
Read R8
T8 TXDIR TXINV ORIE NEIE FEIE PEIE
Write
Reset
0 0 0 0 0 0 0 0
UARTx_C3 field descriptions
Field Description
7
R8
Ninth Data Bit for Receiver
When the UART is configured for 9-bit data (M = 1), R8 can be thought of as a ninth receive data bit to the
left of the msb of the buffered data in the UART_D register. When reading 9-bit data, read R8 before
reading UART_D because reading UART_D completes automatic flag clearing sequences that could allow
R8 and UART_D to be overwritten with new data.
6
T8
Ninth Data Bit for Transmitter
When the UART is configured for 9-bit data (M = 1), T8 may be thought of as a ninth transmit data bit to
the left of the msb of the data in the UART_D register. When writing 9-bit data, the entire 9-bit value is
transferred to the UART shift register after UART_D is written so T8 should be written, if it needs to
change from its previous value, before UART_D is written. If T8 does not need to change in the new value,
Table continues on the next page...
Register definition
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
758 Freescale Semiconductor, Inc.