NXP Semiconductors KL25 Series - Chapter 3 Chip Configuration; 3.2 Module to Module Interconnects

Chapter 3
Chip Configuration
3.1 Introduction
This chapter provides details on the individual modules of the microcontroller. It
includes:
• Module block diagrams showing immediate connections within the device
• Specific module-to-module interactions not necessarily discussed in the individual
module chapters
• Links for more information
Module to Module Interconnects
3.2.1 Module to Module Interconnects
The below table captures the Module to module interconnections for this device.
Table 3-1. Module to Module Interconnects
Peripheral Signal — to Peripheral Use Case Control Comment
TPM1 CH0F, CH1F to ADC (Trigger) ADC Triggering
(A AND B)
SOPT7_ADCAL
TTRGEN = 0
Ch0 is A, and
Ch1 is B,
selecting this
ADC trigger is
for supporting A
and B triggering.
In Stop and
VLPS modes,
the second
trigger must be
set to >10us
after the first
trigger
Table continues on the next page...
3.2
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 45