40.3.3.1 Data sampling technique
The UART receiver uses a 16× baud rate clock for sampling. The receiver starts by
taking logic level samples at 16 times the baud rate to search for a falling edge on the
RxD serial data input pin. A falling edge is defined as a logic 0 sample after three
consecutive logic 1 samples. The 16× baud rate clock divides the bit time into 16
segments labeled UART_D[[RT1] through UART_D[RT16]. When a falling edge is
located, three more samples are taken at UART_D[RT3], UART_D[RT5], and
UART_D[RT7] to make sure this was a real start bit and not merely noise. If at least two
of these three samples are 0, the receiver assumes it is synchronized to a receive
character.
The receiver then samples each bit time, including the start and stop bits, at
UART_D[RT8], UART_D[RT9], and UART_D[RT10] to determine the logic level for
that bit. The logic level is interpreted to be that of the majority of the samples taken
during the bit time. In the case of the start bit, the bit is assumed to be 0 if at least two of
the samples at UART_D[RT3], UART_D[RT5], and UART_D[RT7] are 0 even if one or
all of the samples taken at UART_D[RT8], UART_D[RT9], and UART_D[RT10] are 1s.
If any sample in any bit time, including the start and stop bits, in a character frame fails to
agree with the logic level for that bit, the noise flag (UART_S1[NF]) is set when the
received character is transferred to the receive data buffer.
The falling edge detection logic continuously looks for falling edges. If an edge is
detected, the sample clock is resynchronized to bit times. This improves the reliability of
the receiver in the presence of noise or mismatched baud rates. It does not improve worst
case analysis because some characters do not have any extra falling edges anywhere in
the character frame.
In the case of a framing error, provided the received character was not a break character,
the sampling logic that searches for a falling edge is filled with three logic 1 samples so
that a new start bit can be detected almost immediately.
In the case of a framing error, the receiver is inhibited from receiving any new characters
until the framing error flag is cleared. The receive shift register continues to function, but
a complete character cannot transfer to the receive data buffer if UART_S1[FE] remains
set.
Chapter 40 Universal Asynchronous Receiver/Transmitter (UART1 and UART2)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 765
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